from svg_schematic import Schematic, Label, Resistor, Wire, with_x
from inform import Error, error, os_error
try:
with Schematic(
filename='wires.svg',
background='none',
line_width=2,
):
r11 = Resistor(orient='h')
r12 = Resistor(orient='h', n=r11.p, off=(50, 50))
w = Wire([r11.p, r12.n], kind='plain')
c = with_x(w.m, r12.E)
Label(name="kind='plain'", C=c, xoff=25, loc='e', w=5)
r21 = Resistor(orient='h', C=r11.C, yoff=100)
r22 = Resistor(orient='h', n=r21.p, off=(50, 50))
w = Wire([r21.p, r22.n], kind='|-')
c = with_x(w.m, r22.E)
Label(name="kind='|-'", C=c, xoff=25, loc='e', w=5)
r31 = Resistor(orient='h', C=r21.C, yoff=100)
r32 = Resistor(orient='h', n=r31.p, off=(50, 50))
w = Wire([r31.p, r32.n], kind='-|')
c = with_x(w.m, r32.E)
Label(name="kind='-|'", C=c, xoff=25, loc='e', w=5)
r41 = Resistor(orient='h', C=r31.C, yoff=100)
r42 = Resistor(orient='h', n=r41.p, off=(50, 50))
w = Wire([r41.p, r42.n], kind='|-|')
c = with_x(w.m, r42.E)
d3 = Diode(a=d2.c, xoff=50, orient='h')
c3 = Capacitor(p=d3.c, off=(25, 25), orient='v')
d4 = Diode(a=d3.c, xoff=50, orient='h')
c4 = Capacitor(p=d4.c, off=(25, 25), orient='v')
d5 = Diode(a=d4.c, xoff=50, orient='h')
c5 = Capacitor(p=d5.c, off=(25, 25), orient='v')
vout = Pin(C=d5.c, xoff=75, kind='out', name=r'$V_{\rm out}$', w=2)
Ground(t=c5.n)
Wire([vin.t, d1.a])
Wire([d1.c, d2.a])
Wire([d2.c, d3.a])
Wire([d3.c, d4.a])
Wire([d4.c, d5.a])
Wire([d5.c, vout.t])
Wire([with_x(vin.t, c1.C), c1.p])
Wire([with_x(vin.t, c2.C), c2.p])
Wire([with_x(vin.t, c3.C), c3.p])
Wire([with_x(vin.t, c4.C), c4.p])
Wire([with_x(vin.t, c5.C), c5.p])
Wire([p1.t, c1.n], kind='-|')
Wire([p2.t, c2.n], kind='-|')
co = Dot(C=with_x(p1.C, c2.C), color='white') # wire cross over
Wire([p1.t, c3.n], kind='-|')
Wire([p2.t, c4.n], kind='-|')
except Error as e:
e.report()
except OSError as e:
error(os_error(e))
cmp = Amp(pi=amp.o, xoff=125, kind='comp', name='cmp')
Wire([amp.o, cmp.pi])
gd = Box(i=cmp.o, xoff=50, name='gate', value='drivers')
Wire([cmp.o, gd.i])
pfet = MOS(g=gd.N, yoff=-50, kind='p', orient='h')
Wire([pfet.g, gd.N])
Wire([pfet.s, pvdd.C])
nfet = MOS(g=gd.o, xoff=25, kind='n', orient='v')
Wire([nfet.g, gd.o])
Wire([nfet.d, pfet.d], kind='|-')
Ground(C=nfet.s)
ind = Inductor(n=with_x(pfet.d, nfet.E), orient='h')
Wire([pfet.d, ind.n])
cap = Capacitor(p=ind.p, orient='v')
Ground(C=cap.n)
out = Pin(C=ind.p, xoff=100, kind='out', name='out', w=2)
out_wire = Wire([ind.p, out.C])
fb = shift_y(R1.n, 100)
Rt = Resistor(n=with_x(fb, out_wire.m), orient='v')
Rb = Resistor(p=with_x(fb, out_wire.m), orient='v')
Wire([Rt.p, with_y(Rt.p, out.C)])
Ground(C=Rb.n)
RG = Box(o=C1.n, yoff=175)
rg2cmp = Wire([RG.o, cmp.ni], kind='-|-')
from inform import Error, error, os_error
try:
with Schematic(filename='pipeline-adc.svg', line_width=2):
# Stage 1
i = Pin(kind='in', name='in')
s1 = Box(NW=i.t,
off=(25, -62.5),
w=10.5,
h=4.5,
background='lightgray')
Label(C=s1.SE, loc='nw', name='Stage 1')
adc = Box(W=i.t, off=(75, 100), name='2 bit', value='Flash')
dac = Box(i=adc.o, xoff=50, name='2 bit', value='DAC')
sh = Box(C=with_x(i.t, midpoint(adc.C, dac.C)), name='SAH')
sum = Source(W=with_x(i.t, dac.E), xoff=25, kind='sum', orient='h|')
Label(C=sum.W, loc='nw', name='+')
Label(C=sum.S, loc='se', name='−')
amp = Amp(i=sum.E, xoff=25, kind='se', name='4×')
Wire([i.t, sh.i])
Wire([sh.o, sum.W])
Wire([sum.E, amp.i])
Wire([shift_x(i.t, 50), adc.i], kind='|-')
Wire([adc.o, dac.i])
Wire([dac.o, sum.S], kind='-|')
# Stages 2, 3, 4
s2 = Box(N=dac.S, off=(25, 75), name='Stage 2')
s3 = Box(W=s2.E, xoff=50, name='Stage 3')
s4 = Box(W=s3.E, xoff=50, name='4 bit', value='Flash')