def test_fast_group_adder_1(self): wires, vals = utils.make_wires_and_values(max_bitwidth=12, num_wires=7) outwire = pyrtl.Output(name="test") outwire <<= adders.fast_group_adder(wires) out_vals = utils.sim_and_ret_out(outwire, wires, vals) true_result = [sum(cycle_vals) for cycle_vals in zip(*vals)] self.assertEqual(out_vals, true_result)
def adder_t_base(self, adder_func, **kwargs): wires, vals = utils.make_wires_and_values(**kwargs) outwire = pyrtl.Output(name="test") outwire <<= adder_func(*wires) out_vals = utils.sim_and_ret_out(outwire, wires, vals) true_result = [sum(cycle_vals) for cycle_vals in zip(*vals)] self.assertEqual(out_vals, true_result)
def mux_t_subprocess(self, addr_width, val_width): mux_ins, vals = utils.make_consts(num_wires=2 ** addr_width, exact_bitwidth=val_width) control, testctrl = utils.generate_in_wire_and_values(addr_width, 40, "mux_ctrl") out = pyrtl.Output(val_width, "mux_out") out <<= libutils.basic_n_bit_mux(control, mux_ins) true_result = [vals[i] for i in testctrl] mux_result = utils.sim_and_ret_out(out, (control,), (testctrl,)) self.assertEqual(mux_result, true_result)
def mux_t_subprocess(self, addr_width, val_width): mux_ins, vals = utils.make_consts(num_wires=2**addr_width, exact_bitwidth=val_width) control, testctrl = utils.generate_in_wire_and_values( addr_width, 40, "mux_ctrl") out = pyrtl.Output(val_width, "mux_out") out <<= libutils.basic_n_bit_mux(control, mux_ins) true_result = [vals[i] for i in testctrl] mux_result = utils.sim_and_ret_out(out, (control, ), (testctrl, )) self.assertEqual(mux_result, true_result)
def test_fma_1(self): wires, vals = utils.make_wires_and_values(exact_bitwidth=10, num_wires=3) test_w = multipliers.fused_multiply_adder(wires[0], wires[1], wires[2], False, reducer=adders.dada_reducer, adder_func=adders.ripple_add) self.assertEqual(len(test_w), 20) outwire = pyrtl.Output(21, "test") outwire <<= test_w out_vals = utils.sim_and_ret_out(outwire, wires, vals) true_result = [vals[0][cycle] * vals[1][cycle] + vals[2][cycle] for cycle in range(len(vals[0]))] self.assertEqual(out_vals, true_result)
def test_gen_fma_1(self): wires, vals = utils.make_wires_and_values(max_bitwidth=8, num_wires=8) # mixing tuples and lists solely for readability purposes mult_pairs = [(wires[0], wires[1]), (wires[2], wires[3]), (wires[4], wires[5])] add_wires = (wires[6], wires[7]) outwire = pyrtl.Output(name="test") outwire <<= multipliers.generalized_fma(mult_pairs, add_wires, signed=False) out_vals = utils.sim_and_ret_out(outwire, wires, vals) true_result = [vals[0][cycle] * vals[1][cycle] + vals[2][cycle] * vals[3][cycle] + vals[4][cycle] * vals[5][cycle] + vals[6][cycle] + vals[7][cycle] for cycle in range(len(vals[0]))] self.assertEqual(out_vals, true_result)