class NetSoC(BaseSoC):
csr_peripherals = (
"ethphy",
"ethmac",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
interrupt_map = {
"ethmac": 3,
}
interrupt_map.update(BaseSoC.interrupt_map)
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, platform, *args, **kwargs):
# Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
if 'integrated_rom_size' not in kwargs and kwargs.get(
'cpu_type', 'lm32') == 'or1k':
kwargs['integrated_rom_size'] = 0x10000
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
#self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
40.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
40.0)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def configure_iprange(self, iprange):
iprange = [int(x) for x in iprange.split(".")]
while len(iprange) < 4:
iprange.append(0)
# Our IP address
self._configure_ip("LOCALIP", iprange[:-1] + [50])
# IP address of tftp host
self._configure_ip("REMOTEIP", iprange[:-1] + [100])
def _configure_ip(self, ip_type, ip):
for i, e in enumerate(ip):
s = ip_type + str(i + 1)
s = s.upper()
self.add_constant(s, e)
class BaseSoC(SoCSDRAM):
csr_peripherals = ("ddrphy", )
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
def __init__(self, platform, **kwargs):
clk_freq = (31 + Fraction(1, 4)) * 1000 * 1000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
# sdram
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=2,
wr_bitslip=3,
dqs_ddr_alignment="C1")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
class MemTestSoC(BaseSoC):
csr_peripherals = (
"generator",
"checker",
"checker_scope",
"analyzer",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.generator = LiteDRAMBISTGenerator(
self.sdram.crossbar.get_port(
mode="write",
data_width=32,
),
random=False,
)
self.submodules.checker = LiteDRAMBISTChecker(
self.sdram.crossbar.get_port(
mode="read",
data_width=32,
reverse=True,
),
random=False,
)
self.submodules.checker_scope = LiteDRAMBISTCheckerScope(self.checker)
analyzer_signals = self.checker_scope.signals()
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024)
def do_exit(self, vns, filename="test/analyzer.csv"):
self.analyzer.export_csv(vns, filename)
class BaseSoC(SoCSDRAM):
csr_peripherals = (
"spiflash",
"front_panel",
"ddrphy",
"info",
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
mem_map = {
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}
mem_map.update(SoCSDRAM.mem_map)
def __init__(self, platform, **kwargs):
clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash4x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
# sdram
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
class BaseSoC(SoCSDRAM):
csr_peripherals = (
,
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
mem_map = {
"firmware_ram": 0x20000000, # (default shadow @0xa0000000)
}
mem_map.update(SoCSDRAM.mem_map)
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size']=0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size']=0x8000
if 'firmware_ram_size' not in kwargs:
kwargs['firmware_ram_size']=0x10000
if 'firmware_filename' not in kwargs:
kwargs['firmware_filename'] = "build/sim_{}_{}/software/firmware/firmware.fbi".format(
self.__class__.__name__.lower()[:-3], kwargs.get('cpu_type', 'lm32'))
clk_freq = int((1/(platform.default_clk_period))*1000000000)
SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy)
# firmware
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.flash_boot_address = self.mem_map["firmware_ram"]
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
# sdram
sdram_module = IS42S16160(self.clk_freq, "1:1")
phy_settings = PhySettings(
memtype="SDR",
dfi_databits=1*32,
nphases=1,
rdphase=0,
wrphase=0,
rdcmdphase=0,
wrcmdphase=0,
cl=2,
read_latency=4,
write_latency=0
)
self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
controller_settings = ControllerSettings(with_refresh=False)
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
# reduce memtest size to speed up simulation
self.add_constant("MEMTEST_DATA_SIZE", 1024)
self.add_constant("MEMTEST_ADDR_SIZE", 1024)
self.add_constant("SIMULATION", 1)
class BaseSoC(SoCSDRAM):
csr_peripherals = (
"ddrphy",
"info",
"cas",
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
mem_map = {
"emulator_ram": 0x50000000, # (default shadow @0xd0000000)
}
mem_map.update(SoCSDRAM.mem_map)
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
clk_freq = int(50e6)
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
gmii_rst_n = platform.request("gmii_rst_n")
self.comb += [gmii_rst_n.eq(1)]
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
# sdram
sdram_module = MT47H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram_b"),
sdram_module.memtype,
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
class BaseSoC(SoCSDRAM):
csr_peripherals = (
"ddrphy",
"generator",
"checker",
"info",
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="NeTV2 LiteX Base SoC",
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
#self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
# sdram
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(
platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 8)
controller_settings = ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
# common led
self.sys_led = Signal()
self.pcie_led = Signal()
self.comb += platform.request("user_led", 0).eq(self.sys_led ^ self.pcie_led)
#checker_port = self.sdram.crossbar.get_port(mode="read")
#self.submodules.checker = LiteDRAMBISTChecker(checker_port)
# led blink
#counter = Signal(32)
#self.sync.clk125 += counter.eq(counter + 1)
#self.comb += platform.request("user_led", 0).eq(counter[26])
# sys led
sys_counter = Signal(32)
self.sync += sys_counter.eq(sys_counter + 1)
self.comb += self.sys_led.eq(sys_counter[26])
class AxiomSoC(BaseSoC):
csr_peripherals = (
"gpio",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, tofe_board='tofe2axiom', **kwargs)
self.submodules.gpio = GPIO2TOFE(platform.request("tofe", 0))
class BaseSoC(SoCCore):
csr_peripherals = (
"spiflash",
"info",
)
csr_map_update(SoCCore.csr_map, csr_peripherals)
mem_map = {
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}
mem_map.update(SoCCore.mem_map)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
clk_freq = int(100e6)
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
16 * 1024 * 1024)
class EtherboneSoC(SoCCore):
csr_peripherals = (
"ethphy",
"ethcore",
)
csr_map_update(SoCCore.csr_map, csr_peripherals)
def __init__(self,
platform,
cpu_type=None,
mac_address=0x10e2d5000000,
ip_address="192.168.100.50",
**kwargs):
clk_freq = int(142e6)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
integrated_main_ram_size=0x8000,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
csr_data_width=32,
with_uart=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# ethernet mac/udp/ip stack
self.submodules.ethphy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"), self.platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address,
convert_ip(ip_address),
self.clk_freq,
with_icmp=True)
# etherbone bridge
self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 1234))
self.add_wb_master(self.cpu_or_bridge.wishbone.bus)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
period_ns(125e6))
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
period_ns(125e6))
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
class NetSoC(BaseSoC):
csr_peripherals = (
"ethphy",
"ethmac",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
interrupt_map = {
"ethmac": 3,
}
interrupt_map.update(BaseSoC.interrupt_map)
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(
platform.request("eth_clocks"),
platform.request("eth"))
self.platform.add_source("gateware/rgmii_if.vhd")
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
#self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
#self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk)
# self.ethphy.crg.cd_eth_tx.clk)
def configure_iprange(self, iprange):
iprange = [int(x) for x in iprange.split(".")]
while len(iprange) < 4:
iprange.append(0)
# Our IP address
self._configure_ip("LOCALIP", iprange[:-1]+[50])
# IP address of tftp host
self._configure_ip("REMOTEIP", iprange[:-1]+[100])
def _configure_ip(self, ip_type, ip):
for i, e in enumerate(ip):
s = ip_type + str(i + 1)
s = s.upper()
self.add_constant(s, e)
class BaseSoC(SoCSDRAM):
csr_peripherals = (
"spiflash",
"cas",
"ddrphy",
"info",
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
mem_map = {
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}
mem_map.update(SoCSDRAM.mem_map)
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x4000
clk_freq = 80 * 1000000
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash2x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
# sdram
sdram_module = AS4C16M16(self.clk_freq, "1:1")
self.submodules.ddrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
class VideoSoC(BaseSoC):
csr_peripherals = {
"video_out": 20,
}
csr_map_update(BaseSoC.csr_map, csr_peripherals)
def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.submodules.video_out = VideoOutCore(
self.sdram.crossbar.get_port())
self.submodules.vga = VGAModel(platform.request("vga"))
self.comb += self.video_out.source.connect(self.vga.sink)
class MemTestSoC(BaseSoC):
csr_peripherals = (
"generator",
"checker",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.generator = LiteDRAMBISTGenerator(
self.sdram.crossbar.get_port(mode="write"))
#self.submodules.checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port(mode="read", dw=16)) #, cd="hdmi_out1_pix"))
self.submodules.checker = LiteDRAMBISTChecker(
self.sdram.crossbar.get_port(mode="read")) #, cd="hdmi_out1_pix"))
class VideoSoCDebug(VideoSoC):
csr_peripherals = (
"analyzer",
)
csr_map_update(VideoSoC.csr_map, csr_peripherals)
def __init__(self, platform, *args, **kwargs):
VideoSoC.__init__(self, platform, *args, **kwargs)
# # #
# analyzer
analyzer_signals = [
self.hdmi_in0.data0_charsync.raw_data,
self.hdmi_in0.data1_charsync.raw_data,
self.hdmi_in0.data2_charsync.raw_data,
self.hdmi_in0.data0_charsync.synced,
self.hdmi_in0.data1_charsync.synced,
self.hdmi_in0.data2_charsync.synced,
self.hdmi_in0.data0_charsync.data,
self.hdmi_in0.data1_charsync.data,
self.hdmi_in0.data2_charsync.data,
self.hdmi_in0.syncpol.valid_o,
self.hdmi_in0.syncpol.de,
self.hdmi_in0.syncpol.hsync,
self.hdmi_in0.syncpol.vsync,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024, cd="hdmi_in0_pix", cd_ratio=2)
# leds
pix_counter = Signal(32)
self.sync.hdmi_in0_pix += pix_counter.eq(pix_counter + 1)
self.comb += platform.request("user_led", 0).eq(pix_counter[26])
pix1p25x_counter = Signal(32)
self.sync.pix1p25x += pix1p25x_counter.eq(pix1p25x_counter + 1)
self.comb += platform.request("user_led", 1).eq(pix1p25x_counter[26])
pix5x_counter = Signal(32)
self.sync.hdmi_in0_pix5x += pix5x_counter.eq(pix5x_counter + 1)
self.comb += platform.request("user_led", 2).eq(pix5x_counter[26])
def do_exit(self, vns):
self.analyzer.export_csv(vns, "test/analyzer.csv")
class HDMI2USBSoC(BaseSoC):
csr_peripherals = (
"encoder_reader",
"encoder",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
mem_map = {
"encoder": 0x50000000, # (shadow @0xd0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
encoder_port = self.sdram.crossbar.get_port(
mode="read",
data_width=128,
reverse=True,
)
self.submodules.encoder_reader = EncoderDMAReader(encoder_port)
encoder_cdc = stream.AsyncFIFO([("data", 128)], 4)
encoder_cdc = ClockDomainsRenamer({
"write": "sys",
"read": "encoder"
})(encoder_cdc)
encoder_buffer = ClockDomainsRenamer("encoder")(EncoderBuffer())
encoder = Encoder(platform)
encoder_streamer = USBStreamer(platform, platform.request("fx2"))
self.submodules += encoder_cdc, encoder_buffer, encoder, encoder_streamer
self.comb += [
self.encoder_reader.source.connect(encoder_cdc.sink),
encoder_cdc.source.connect(encoder_buffer.sink),
encoder_buffer.source.connect(encoder.sink),
encoder.source.connect(encoder_streamer.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]), encoder.bus)
self.add_memory_region("encoder",
self.mem_map["encoder"] + self.shadow_base,
0x2000)
self.platform.add_period_constraint(encoder_streamer.cd_usb.clk, 10.0)
encoder_streamer.cd_usb.clk.attr.add("keep")
self.crg.cd_encoder.clk.attr.add("keep")
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.crg.cd_encoder.clk,
encoder_streamer.cd_usb.clk)
class BridgeSoC(BaseSoC):
csr_peripherals = (
"analyzer",
"io",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
def __init__(self, platform, *args, **kwargs):
kwargs['cpu_type'] = None
BaseSoC.__init__(self, platform, *args, with_uart=False, **kwargs)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
self.clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
class BaseSoC(SoCSDRAM):
csr_peripherals = (
"spiflash",
"info",
"cas",
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
SoCSDRAM.mem_map = {
"rom": 0x00000000,
"sram": 0x10000000,
"main_ram": 0x40000000,
"csr": 0xe0000000,
}
mem_map = {
"spiflash": 0x20000000,
"emulator_ram": 0x50000000,
}
mem_map.update(SoCSDRAM.mem_map)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
if 'integrated_main_ram_size' not in kwargs:
kwargs['integrated_main_ram_size'] = 0x20000
clk_freq = int(50e6)
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
class BaseSoC(SoCSDRAM):
csr_peripherals = (
"spiflash",
"ddrphy",
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
def __init__(self, platform, **kwargs):
clk_freq = 50 * 1000000
if 'expansion' in kwargs:
tofe_board_name = kwargs.get('expansion')
del kwargs['expansion']
else:
tofe_board_name = None
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
with_uart=True,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
# sdram
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(
platform.request("ddram"),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb),
self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb),
]
class MemTestSoC(BaseSoC):
csr_peripherals = (
"generator",
"checker",
"checker_scope",
"analyzer",
"io",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, with_uart=False, **kwargs)
# Memory test BIST
self.submodules.generator = LiteDRAMBISTGenerator(
self.sdram.crossbar.get_port(mode="write", data_width=32))
self.submodules.checker = LiteDRAMBISTChecker(
self.sdram.crossbar.get_port(mode="read", data_width=32))
self.submodules.checker_scope = LiteDRAMBISTCheckerScope(self.checker)
# Litescope for analyzing the BIST output
# --------------------
# Dummy UART
self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200)
self.submodules.uart = self.suart.uart
self.submodules.uartbridge = UARTWishboneBridge(
platform.request("serial"), self.clk_freq, baudrate=19200)
self.add_wb_master(self.uartbridge.wishbone)
# self.submodules.io = LiteScopeIO(8)
# for i in range(8):
# try:
# self.comb += platform.request("user_led", i).eq(self.io.output[i])
# except:
# pass
analyzer_signals = self.checker_scope.signals()
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 64)
def do_exit(self, vns, filename="test/analyzer.csv"):
self.analyzer.export_csv(vns, filename)
class NetSoC(BaseSoC):
csr_peripherals = (
"ethphy",
"ethmac",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self,
platform,
integrated_rom_size=0x10000,
*args,
**kwargs)
self.submodules.ethphy = LiteEthPHYRMII(platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
40.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
40.0)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
self.add_interrupt("ethmac")
class MemTestSoC(BaseSoC):
csr_peripherals = (
"analyzer",
"io",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
def __init__(self, platform, *args, **kwargs):
kwargs['cpu_type'] = None
BaseSoC.__init__(self, platform, *args, with_uart=False, **kwargs)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
self.clk_freq,
baudrate=19200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# Litescope for analyzing the BIST output
# --------------------
self.submodules.io = LiteScopeIO(8)
for i in range(8):
try:
self.comb += platform.request("user_led",
i).eq(self.io.output[i])
except:
pass
analyzer_signals = [
self.spiflash.bus,
# self.spiflash.cs_n,
# self.spiflash.clk,
# self.spiflash.dq_oe,
# self.spiflash.dqi,
# self.spiflash.sr,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024)
def do_exit(self, vns, filename="test/analyzer.csv"):
self.analyzer.export_csv(vns, filename)
class BaseSoC(SoCSDRAM):
csr_peripherals = (
"spiflash",
"front_panel",
"ddrphy",
"info",
"fx2_reset",
"fx2_hack",
"tofe",
"opsis_i2c",
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
mem_map = {
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}
mem_map.update(SoCSDRAM.mem_map)
def __init__(self, platform, **kwargs):
clk_freq = 50 * 1000000
if 'tofe_board' in kwargs:
tofe_board_name = kwargs.get('tofe_board')
del kwargs['tofe_board']
else:
tofe_board_name = None
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
self.submodules.info = info.Info(platform, "opsis",
self.__class__.__name__[:8])
self.submodules.opsis_i2c = opsis_i2c.OpsisI2C(platform)
self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200)
self.suart.add_uart_pads(platform.request('fx2_serial'))
self.submodules.uart = self.suart.uart
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash4x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
# front panel (ATX)
self.submodules.front_panel = FrontPanelGPIO(platform, clk_freq)
self.comb += self.crg.reset.eq(self.front_panel.reset)
# sdram
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(
platform.request("ddram"),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb),
self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb),
]
if tofe_board_name:
if tofe_board_name == 'lowspeedio':
self.submodules.tofe = tofe.TOFEBoard(tofe_board_name)(
platform, self.suart)
else:
self.submodules.tofe = tofe.TOFEBoard(tofe_board_name)(
platform)
class NetSoC(BaseSoC):
csr_peripherals = (
"ethphy",
"ethmac",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
interrupt_map = {
"ethmac": 3,
}
interrupt_map.update(BaseSoC.interrupt_map)
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, platform, *args, **kwargs):
# Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
if 'integrated_rom_size' not in kwargs and kwargs.get('cpu_type', 'lm32') == 'or1k':
kwargs['integrated_rom_size'] = 0x10000
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.ethphy = LiteEthPHY(
platform.request("eth_clocks"),
platform.request("eth"),
self.clk_freq)
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
# FIXME: This is probably too tight?
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk)
self.platform.add_platform_command("""
# FIXME: ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have
# been found that are not placed at an optimal clock IOB / BUFGMUX site pair.
# The clock IOB component <eth_clocks_rx> is placed at site <K15>.
NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE;
# The IOB component <eth_clocks_tx> is placed at site <K16>.
NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE;
""",
eth_clocks_rx=platform.lookup_request("eth_clocks").rx,
eth_clocks_tx=platform.lookup_request("eth_clocks").tx,
)
def configure_iprange(self, iprange):
iprange = [int(x) for x in iprange.split(".")]
while len(iprange) < 4:
iprange.append(0)
# Our IP address
self._configure_ip("LOCALIP", iprange[:-1]+[50])
# IP address of tftp host
self._configure_ip("REMOTEIP", iprange[:-1]+[100])
def _configure_ip(self, ip_type, ip):
for i, e in enumerate(ip):
s = ip_type + str(i + 1)
s = s.upper()
self.add_constant(s, e)
class BaseSoC(SoCCore):
csr_peripherals = (
"spiflash",
"cas",
)
csr_map_update(SoCCore.csr_map, csr_peripherals)
mem_map = {
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}
mem_map.update(SoCCore.mem_map)
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0
# FIXME: Force either lite or minimal variants of CPUs; full is too big.
# Assume user still has LEDs/Buttons still attached to the PCB or as
# a PMOD; pinout is identical either way.
platform.add_extension(icebreaker.break_off_pmod)
clk_freq = int(12e6)
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
# Control and Status
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# SPI flash peripheral
# TODO: Inferred tristate not currently supported by nextpnr; upgrade
# to spiflash4x when possible.
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div,
endianness=self.cpu.endianness)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
# rgb led connector
platform.add_extension(icebreaker.rgb_led)
self.submodules.rgbled = ice40.LED(platform.request("rgbled", 0))
self.add_csr("rgbled")
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom",
kwargs['cpu_reset_address'],
bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
# free up scarce block RAM.
self.submodules.spram = ice40.SPRAM(size=128 * 1024)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
0x20000)
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region(
"user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size -
(self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
type="cached+linker")
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[
3] = "icepack -s {build_name}.txt {build_name}.bin"
platform.toolchain.nextpnr_build_template[
2] = "icepack -s {build_name}.txt {build_name}.bin"
class VideoSoC(BaseSoC):
csr_peripherals = (
"hdmi_out0",
"hdmi_out1",
"hdmi_in0",
"hdmi_in0_edid_mem",
"hdmi_in1",
"hdmi_in1_edid_mem",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
interrupt_map = {
"hdmi_in0": 4,
"hdmi_in1": 5,
}
interrupt_map.update(BaseSoC.interrupt_map)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# hdmi in 0
self.submodules.hdmi_in0 = HDMIIn(
platform.request("hdmi_in", 0),
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512)
# hdmi in 1
self.submodules.hdmi_in1 = HDMIIn(
platform.request("hdmi_in", 1),
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512)
# hdmi out 0
self.submodules.hdmi_out0 = VideoOut(platform.device,
platform.request("hdmi_out", 0),
self.sdram.crossbar.get_port(
mode="read",
dw=16,
cd="hdmi_out0_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=4096)
# hdmi out 1 : Share clocking with hdmi_out0 since no PLL_ADV left.
self.submodules.hdmi_out1 = VideoOut(
platform.device,
platform.request("hdmi_out", 1),
self.sdram.crossbar.get_port(mode="read",
dw=16,
cd="hdmi_out1_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=4096,
external_clocking=self.hdmi_out0.driver.clocking)
# all PLL_ADV are used: router needs help...
platform.add_platform_command("""INST crg_pll_adv LOC=PLL_ADV_X0Y0;""")
# FIXME: Fix the HDMI out so this can be removed.
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg_1.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
# We have CDC to go from sys_clk to pixel domain
platform.add_platform_command(
"""
NET "{pix0_clk}" TNM_NET = "GRPpix0_clk";
NET "{pix1_clk}" TNM_NET = "GRPpix1_clk";
""",
pix0_clk=self.hdmi_out0.driver.clocking.cd_pix.clk,
pix1_clk=self.hdmi_out1.driver.clocking.cd_pix.clk,
)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix.clk)
for name, value in sorted(self.platform.hdmi_infos.items()):
self.add_constant(name, value)
class BaseSoC(SoCCore):
csr_peripherals = (
"spiflash",
"cas",
)
csr_map_update(SoCCore.csr_map, csr_peripherals)
mem_map = {
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}
mem_map.update(SoCCore.mem_map)
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x2800
# FIXME: Force either lite or minimal variants of CPUs; full is too big.
clk_freq = int(12e6)
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
# Control and Status
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# SPI flash peripheral
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom",
kwargs['cpu_reset_address'],
bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region(
"user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size -
(self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
type="cached+linker")
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[
3] = "icepack -s {build_name}.txt {build_name}.bin"
platform.toolchain.nextpnr_build_template[
2] = "icepack -s {build_name}.txt {build_name}.bin"
class BaseSoC(SoCSDRAM):
csr_peripherals = (
"spiflash",
"ddrphy",
"info",
"oled",
"uart",
"uart_phy",
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
mem_map = {
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}
mem_map.update(SoCSDRAM.mem_map)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size']=0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size']=0x8000
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq))
uart_interfaces = [RS232PHYInterface() for i in range(2)]
self.submodules.uart = UART(uart_interfaces[0])
self.submodules.bridge = WishboneStreamingBridge(uart_interfaces[1], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200)
self.submodules.uart_multiplexer = RS232PHYMultiplexer(uart_interfaces, self.uart_phy)
self.comb += self.uart_multiplexer.sel.eq(platform.request("user_sw", 0))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.oled = oled.OLED(platform.request("oled"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads,
dummy=spiflash_dummy[spiflash],
div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)
self.add_memory_region(
"spiflash", self.mem_map["spiflash"], 16*1024*1024)
self.add_interrupt("uart")
class VideoSoC(BaseSoC):
csr_peripherals = (
"hdmi_out0",
"hdmi_in0",
"hdmi_in0_freq",
"hdmi_in0_edid_mem",
)
csr_map_update(BaseSoC.csr_map, csr_peripherals)
interrupt_map = {
"hdmi_in0": 4,
}
interrupt_map.update(BaseSoC.interrupt_map)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
mode = "ycbcr422"
if mode == "ycbcr422":
dw = 16
elif mode == "rgb":
dw = 32
else:
raise SystemError("Unknown pixel mode.")
pix_freq = 148.50e6
# hdmi in 0
hdmi_in0_pads = platform.request("hdmi_in")
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7")
self.submodules.hdmi_in0_freq = FrequencyMeter(period=self.clk_freq)
self.comb += [
self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk),
hdmi_in0_pads.txen.eq(1)
]
self.platform.add_period_constraint(self.hdmi_in0.clocking.cd_pix.clk,
period_ns(1 * pix_freq))
self.platform.add_period_constraint(
self.hdmi_in0.clocking.cd_pix1p25x.clk, period_ns(1.25 * pix_freq))
self.platform.add_period_constraint(
self.hdmi_in0.clocking.cd_pix5x.clk, period_ns(5 * pix_freq))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk)
# hdmi out 0
hdmi_out0_pads = platform.request("hdmi_out")
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read",
dw=dw,
cd="hdmi_out0_pix",
reverse=True)
self.submodules.hdmi_out0 = VideoOut(platform.device,
hdmi_out0_pads,
hdmi_out0_dram_port,
mode=mode,
fifo_depth=4096)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk)
self.platform.add_period_constraint(
self.hdmi_out0.driver.clocking.cd_pix.clk, period_ns(1 * pix_freq))
self.platform.add_period_constraint(
self.hdmi_out0.driver.clocking.cd_pix5x.clk,
period_ns(5 * pix_freq))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk)
for name, value in sorted(self.platform.hdmi_infos.items()):
self.add_constant(name, value)
class BaseSoC(SoCSDRAM):
csr_peripherals = (
"spiflash",
"ddrphy",
"info",
# "leds",
# "rgb_leds",
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
mem_map = {
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}
mem_map.update(SoCSDRAM.mem_map)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
# self.submodules.leds = led.ClassicLed(Cat(platform.request("user_led", i) for i in range(4)))
# self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
16 * 1024 * 1024)
# sdram
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
controller_settings = ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)