def main():
"""
The tendril-genpcbpricing script entry point.
"""
parser = _get_parser()
args = parser.parse_args()
force = args.force
lazy = args.lazy
if args.all:
regenerate_all(force=force, lazy=lazy, dry_run=args.dry_run)
else:
if not len(args.projfolders):
parser.print_help()
for projfolder in args.projfolders:
if not os.path.isabs(projfolder):
projfolder = os.path.join(os.getcwd(), projfolder)
projfolder = os.path.normpath(projfolder)
if not in_directory(projfolder, PROJECTS_ROOT):
logger.error(
'Provided directory does not seem to be under the '
'tendril PROJECTS_ROOT. Skipping ' + projfolder
)
continue
targets = [projfolder]
if args.recurse:
lprojects, lpcbs, lcards, lcard_reporoot = \
projects.get_projects(projfolder)
targets.extend([lpcbs[x] for x in lpcbs.keys()])
for target in targets:
try:
if args.dry_run is False:
csil.generate_pcb_pricing(
target, forceregen=force, noregen=lazy
)
logger.info("Checked " + target)
else:
conffile.ConfigsFile(target)
logger.info("Will check " + target)
except NoGedaProjectError:
# Make a guess.
if os.path.split(target)[1] == 'configs.yaml':
target == os.path.split(target)[0]
if os.path.split(target)[1] == 'schematic':
target == os.path.split(target)[0]
try:
if args.dry_run is False:
csil.generate_pcb_pricing(
target, forceregen=force, noregen=lazy
)
logger.info("Checked " + target)
else:
conffile.ConfigsFile(target)
logger.info("Will check " + target)
except NoGedaProjectError:
logger.error("No gEDA Project found at " + target)
def dox_regen(wcpath):
log.msg("Regenerate dox for ", wcpath)
targets = []
if projects.is_project_folder(wcpath):
targets.append(wcpath)
lprojects, lpcbs, lcards, lcard_reporoot = \
projects.get_projects(wcpath)
targets.extend([lprojects[x] for x in lprojects.keys()])
for target in targets:
log.msg(" -- Regenerate dox for ", target)
gedaproject.generate_docs(target)
def main():
"""
The tendril-genpcbpricing script entry point.
"""
parser = _get_parser()
args = parser.parse_args()
force = args.force
lazy = args.lazy
if args.all:
regenerate_all(force=force, lazy=lazy, dry_run=args.dry_run)
else:
if not len(args.projfolders):
parser.print_help()
for projfolder in args.projfolders:
if not os.path.isabs(projfolder):
projfolder = os.path.join(os.getcwd(), projfolder)
projfolder = os.path.normpath(projfolder)
if not in_directory(projfolder, PROJECTS_ROOT):
logger.error(
'Provided directory does not seem to be under the '
'tendril PROJECTS_ROOT. Skipping ' + projfolder)
continue
targets = [projfolder]
if args.recurse:
lprojects, lpcbs, lcards, lcard_reporoot = \
projects.get_projects(projfolder)
targets.extend([lpcbs[x] for x in lpcbs.keys()])
for target in targets:
try:
if args.dry_run is False:
csil.generate_pcb_pricing(target,
forceregen=force,
noregen=lazy)
logger.info("Checked " + target)
else:
conffile.ConfigsFile(target)
logger.info("Will check " + target)
except NoGedaProjectError:
# Make a guess.
if os.path.split(target)[1] == 'configs.yaml':
target == os.path.split(target)[0]
if os.path.split(target)[1] == 'schematic':
target == os.path.split(target)[0]
try:
if args.dry_run is False:
csil.generate_pcb_pricing(target,
forceregen=force,
noregen=lazy)
logger.info("Checked " + target)
else:
conffile.ConfigsFile(target)
logger.info("Will check " + target)
except NoGedaProjectError:
logger.error("No gEDA Project found at " + target)
def main():
"""
The tendril-validate script entry point.
"""
import logging
logging.getLogger('tendril.sourcing.electronics').setLevel(logging.WARNING)
logging.getLogger('tendril.utils.www').setLevel(logging.WARNING)
parser = _get_parser()
args = parser.parse_args()
statuses = args.statuses or []
statuses.extend(['Active', 'Prototype', 'Prospective', 'Experimental'])
if args.all:
validate_all(s=args.sourcing, statuses=statuses)
else:
done = False
if args.modules:
for modulename in args.modules:
validate_module(modulename, s=args.sourcing)
done = True
else:
for projfolder in args.projfolders:
if not os.path.isabs(projfolder):
projfolder = os.path.join(os.getcwd(), projfolder)
projfolder = os.path.normpath(projfolder)
if not in_directory(projfolder, PROJECTS_ROOT):
logger.error(
'Provided directory does not seem to be under the '
'tendril PROJECTS_ROOT. Skipp ing ' + projfolder)
continue
targets = [projfolder]
if args.recurse:
lprojects, lpcbs, lcards, lcard_reporoot, lcable_projects = \
projects.get_projects(projfolder)
targets.extend([lprojects[x] for x in lprojects.keys()])
for target in targets:
validate_project(target,
s=args.sourcing,
statuses=statuses)
done = True
if not done:
parser.print_help()