def master(dut, port, num):
# Choose operation types based on port mode
ops_choice = {
"both": ["w", "r"],
"write": ["w"],
"read": ["r"],
}[port.mode]
driver = NativePortDriver(port)
for i in range(n_ops):
bank = prng.randrange(n_banks)
# We will later distinguish data by its row address
row = num
col = 0x20 * num + i
addr = dut.addr_port(bank=bank, row=row, col=col)
addr_iface = dut.addr_iface(row=row, col=col)
if prng.choice(ops_choice) == "w":
yield from driver.write(addr, data=i)
produced[num].append(self.W(bank, addr_iface, data=i, we=0xff))
else:
yield from driver.read(addr)
produced[num].append(self.R(bank, addr_iface, data=None))
for _ in range(8):
yield
def producer(dut, port):
driver = NativePortDriver(port)
for t in transfers:
addr = dut.addr_port(bank=t["bank"], row=t["row"], col=t["col"])
if t["rw"] == self.W:
yield from driver.write(addr, data=t["data"], we=t.get("we", None))
elif t["rw"] == self.R:
data = (yield from driver.read(addr))
reads.append(data)
else:
raise TypeError(t["rw"])
def producer(dut, port, num):
driver = NativePortDriver(port)
addr = dut.addr_port(bank=3, row=0x10 + num, col=0x20 + num)
yield from driver.write(addr, data=0x30 + num)