def tests(self): args = dict(master_id=str(self.master_id or self.mdb.log_id), cvr_seed=str(self.cvr_seed), instances=str(self.instances), max_axes=str(self.max_axes)) if test.plusargs().test_xml: return xmlList(test.plusargs().test_xml, **args) else: return randomList(self.children, self.tst_seed, self.testnames, **args)
def prologue(self): # initialize all the same random.seed(self.cvr_seed) self.cpts = [ coverpoint('%d random coverpoint' % i, self.max_axes).cursor() for i in range(0, self.instances) ] self.master_id = test.plusargs().master_id
def excepthook(type, value, traceback) : import traceback as _traceback warning('Exception encountered : %(type)s', type=str(type)) warning(' %(value)s', value=str(value)) for detail in _traceback.extract_tb(traceback) : warning(detail[-1], file=detail[0], line=detail[1], formatted=True) import test if test.plusargs().debug : warning('Exception encountered, entering pdb as requested') test.test.pdb(traceback) warning('Exception encountered, test will now exit') internal('Exception encountered') # redundant exit sys.exit(1)
def excepthook(type, value, traceback): import traceback as _traceback warning('Exception encountered : %(type)s', type=str(type)) warning(' %(value)s', value=str(value)) for detail in _traceback.extract_tb(traceback): warning(detail[-1], file=detail[0], line=detail[1], formatted=True) import test if test.plusargs().debug: warning('Exception encountered, entering pdb as requested') test.test.pdb(traceback) warning('Exception encountered, test will now exit') internal('Exception encountered') # redundant exit sys.exit(1)
def prologue(self) : # initialize random seed with deterministic value seed = test.plusargs().get('seed', 1) random.seed(seed) simctrl = verilog.scope('example.simctrl_0_u') arr = dict([(i, verilog.scope('example.duv_0_u.arr[%d].arr' % i)) for i in range(1,self.MAX_INSTS)]) # up timeout beyond test time simctrl.direct.sim_ctrl_timeout_i = self.TIMEOUT # reduce time step simctrl.direct.sim_ctrl_cycles_freq_i = 1 for scope in arr.values() : scope.direct.verbose = 0 # display values # register call back cbClk0 = self.cb_fcty(simctrl.sim_ctrl_clk_op.set_type(verilog.vpiInt), simctrl, arr)
def prologue(self): # initialize random seed with deterministic value seed = test.plusargs().get('seed', 1) random.seed(seed) simctrl = verilog.scope('example.simctrl_0_u') arr = dict([(i, verilog.scope('example.duv_0_u.arr[%d].arr' % i)) for i in range(1, self.MAX_INSTS)]) # up timeout beyond test time simctrl.direct.sim_ctrl_timeout_i = self.TIMEOUT # reduce time step simctrl.direct.sim_ctrl_cycles_freq_i = 1 for scope in arr.values(): scope.direct.verbose = 0 # display values # register call back cbClk0 = self.cb_fcty(simctrl.sim_ctrl_clk_op.set_type(verilog.vpiInt), simctrl, arr)
def prologue(self): # initialize all the same random.seed(self.cvr_seed) self.cpts = [coverpoint('%d random coverpoint' % i, self.max_axes).cursor() for i in range(0, self.instances)] self.master_id = test.plusargs().master_id
def testnames(self) : return re.split(r'[+:,]', test.plusargs().get('tests', self.filename()))
def is_master(self) : try : return int(test.plusargs().master) except : return self.mdb.is_root()
def tests(self) : args = dict(master_id=str(self.master_id or self.mdb.log_id), cvr_seed=str(self.cvr_seed), instances=str(self.instances), max_axes=str(self.max_axes)) if test.plusargs().test_xml : return xmlList(test.plusargs().test_xml, **args) else : return randomList(self.children, self.tst_seed, self.testnames, **args)
def testnames(self): return re.split(r'[+:,]', test.plusargs().get('tests', self.filename()))
def is_master(self): try: return int(test.plusargs().master) except: return self.mdb.is_root()
def define(self, bucket) : 'set goal' # no dont cares or illegals bucket.default(goal=10) ################################################################################ class thistest(test.test) : bits=5 size=1<<bits activity='python' block='default' name='coverage capacity test' def prologue(self): cpts = [big_coverpoint('%d big coverpoint' % i, self.size).cursor() for i in range(0,100)] for i in range(0, 99999) : random.choice(cpts)(x=random.getrandbits(self.bits), y=random.getrandbits(self.bits)).incr(random.randrange(10)) def epilogue(self) : self.success() ################################################################################ if __name__ == '__main__' : if test.plusargs().profile : import cProfile cProfile.run('thistest()') else : thistest()
# Copyright (c) 2012, 2013 Rich Porter - see LICENSE for further details import atexit import message import test import verilog def root() : return 'example' simctrl = verilog.scope(root() + '.simctrl_0_u') if test.plusargs().timeout : simctrl.direct.sim_ctrl_timeout_i = verilog.vpiInt(test.plusargs().timeout) # use verilog vpi cbEndOfSimulation callback class cbEndOfSimulation(verilog.callback) : def __init__(self) : verilog.callback.__init__(self, name='PLI end of simulation callback', reason=verilog.callback.cbEndOfSimulation, func=self.execute) def execute(self) : message.note('vpi cbEndOfSimulation') end = cbEndOfSimulation() # show when python interpreter is closed down def finalize() : message.note('finalize') atexit.register(finalize)