def test_cic_interpolate_20(self): cic_delay = 1 cic_order = 4 in_sign = Signature("in", True, bits=16) out_sign = Signature("out", True, bits=16) interp_val = 20 interp = Signal(intbv(interp_val, min=0, max=2**10)) decim = Signal(intbv(1, min=0, max=2**10)) shift_val = cic_shift(len(in_sign.i), len(out_sign.i), interp_val, cic_order, cic_delay) shift = Signal(intbv(shift_val, min=0, max=21)) s = DSPSim( in_sign=in_sign, out_sign=out_sign, ) def test_cic_interpolate_20(): truncated = Signature("truncated", True, bits=8) truncator_0 = truncator(s.clearn, s.clock, s.input, truncated) cic_0 = cic(s.clearn, s.clock, truncated, s.output, #cic_0_out, interp, shift, cic_order=cic_order, cic_delay=cic_delay, sim=None) return cic_0, truncator_0 numsamples = 32 fname = '/home/testa/whitebox/hdl/sin.samples' in_i, in_q = load_quadrature_short_samples(fname, offset=65012, numsamples=numsamples) in_t = np.arange(0, in_i.shape[0]) try: out_i, out_q = s.simulate_quadrature(in_i, in_q, test_cic_interpolate_20, interp=interp) except: #s.plot_chain("cic_interpolate_20_error") #plt.show() raise out_t = np.arange(0, out_i.shape[0]) new_shape = tuple([in_t.shape[i] * interp for i in range(len(in_t.shape))]) assert out_t.shape == new_shape f_cic_interpolate_20 = plt.figure("cic_interpolate_20") f_in = figure_discrete_quadrature("in", (2, 1, 1), f_cic_interpolate_20, in_sign, in_t, in_i, in_q) f_out = figure_discrete_quadrature("out", (2, 1, 2), f_cic_interpolate_20, out_sign, out_t, out_i, out_q) plt.savefig("cic_interp_20.png")
def test_fir_design(self): in_sign = Signature("in", True, bits=9) out_sign = Signature("out", True, bits=9) s = FirSim(in_sign=in_sign, out_sign=out_sign) taps = [int(t) for t in s.design(48e3, 12e3, 1e3, 40.0)] in_c = s.input_signal() in_t = arange(len(in_c)) in_i = [int(i.real * (2**8-1)) for i in in_c] in_q = [int(i.imag * (2**8-1)) for i in in_c] s.verify_design() coeff_ram = Ram2(s.clearn, s.clock, s.clock, data=taps) delay_line_i_ram = Ram(s.clearn, s.clock, s.clock) delay_line_q_ram = Ram(s.clearn, s.clock, s.clock) bypass = Signal(bool(0)) bank1 = Signal(bool(0)) bank0 = Signal(bool(0)) N = Signal(intbv(len(taps), min=0, max=2**7-1)) def test_fir_design(): load_coeff_ram_addr = coeff_ram.port['b'].addr load_coeff_ram_blk = coeff_ram.port['b'].blk load_coeff_ram_wen = coeff_ram.port['b'].wen fir_0 = fir(s.clearn, s.clock, s.input, s.output, coeff_ram.port['a'].addr, coeff_ram.port['a'].din[0], coeff_ram.port['a'].din[1], coeff_ram.port['a'].blk, coeff_ram.port['a'].wen, coeff_ram.port['a'].dout[0], coeff_ram.port['a'].dout[1], delay_line_i_ram.port['a'].addr, delay_line_i_ram.port['a'].din, delay_line_i_ram.port['a'].blk, delay_line_i_ram.port['a'].wen, delay_line_i_ram.port['a'].dout, delay_line_q_ram.port['a'].addr, delay_line_q_ram.port['a'].din, delay_line_q_ram.port['a'].blk, delay_line_q_ram.port['a'].wen, delay_line_q_ram.port['a'].dout, bypass, bank1, bank0, N, sim=s) return fir_0, coeff_ram.rama, coeff_ram.ramb, delay_line_i_ram.ram, delay_line_q_ram.ram out_i, out_q = s.simulate_quadrature(in_i, in_q, test_fir_design, interp=128) out_t = arange(0, out_i.shape[0]) new_shape = tuple([in_t.shape[i] for i in range(len(in_t.shape))]) assert out_t.shape == new_shape f = figure("fir_output") title("fir filter output") f_out = figure_discrete_quadrature('FIR Filter Output', (1, 1, 1), f, s.input, out_t, out_i / (2.**8-1), out_q / (2.**8-1)) savefig('output.png')
def plot_tx(self, name, decim=1): """Plot the transmitter's output.""" f_parent = plt.figure(name + "_tx") f_parent.subplots_adjust(hspace=.5) #plt.title(name + "_tx") y = self.tx(decim=decim) n = len(y) k = np.arange(n) f1 = figure_discrete_quadrature("Signal", (3, 1, 1), f_parent, self.dac_data, k, [i.real for i in y], [i.imag for i in y]) #frq = np.fft.fftfreq(n, 1/sample_rate) #y = [i + 1j * q for i, q in zip (self.tx_i, self.tx_q)] #Y = np.fft.fft(y)/n frq, Y = self.fft_tx() f2 = figure_fft_power("Power", (3, 1, 2), f_parent, frq, Y) f3 = figure_fft_phase("Phase", (3, 1, 3), f_parent, frq, Y)