def test_simulate_fail(self, run_command, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
config = make_config()
self.assertFalse(
simif.simulate("suite_output_path", "test_suite_name", config))
elaborate_args_file = join("suite_output_path", simif.name,
"irun_elaborate.args")
simulate_args_file = join("suite_output_path", simif.name,
"irun_simulate.args")
run_command.assert_has_calls([
mock.call(
[join("prefix", "irun"), "-f",
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env(),
),
mock.call(
[join("prefix", "irun"), "-f",
basename(simulate_args_file)],
cwd=dirname(simulate_args_file),
env=simif.get_env(),
),
])
def test_compile_source_files(self):
simif = create_simulator_interface()
simif.compile_source_file_command.side_effect = iter([["command1"],
["command2"]])
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
write_file("file2.vhd", "")
file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
project.add_manual_dependency(file2, depends_on=file1)
with mock.patch("vunit.sim_if.check_output",
autospec=True) as check_output:
check_output.side_effect = iter(["", ""])
printer = MockPrinter()
simif.compile_source_files(project, printer=printer)
check_output.assert_has_calls([
mock.call(["command1"], env=simif.get_env()),
mock.call(["command2"], env=simif.get_env()),
])
self.assertEqual(
printer.output,
"""\
Compiling into lib: file1.vhd passed
Compiling into lib: file2.vhd passed
Compile passed
""",
)
self.assertEqual(project.get_files_in_compile_order(incremental=True),
[])
def test_simulate_hdlvar(self, run_command, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path,
hdlvar="custom_hdlvar")
config = make_config()
self.assertTrue(
simif.simulate("suite_output_path", "test_suite_name", config))
elaborate_args_file = join("suite_output_path", simif.name,
"irun_elaborate.args")
simulate_args_file = join("suite_output_path", simif.name,
"irun_simulate.args")
run_command.assert_has_calls([
mock.call(
[join("prefix", "irun"), "-f",
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env(),
),
mock.call(
[join("prefix", "irun"), "-f",
basename(simulate_args_file)],
cwd=dirname(simulate_args_file),
env=simif.get_env(),
),
])
for args_file in [elaborate_args_file, simulate_args_file]:
args = read_file(args_file).splitlines()
self.assertIn('-hdlvar "custom_hdlvar"', args)
def test_simulate_generics_and_parameters(self, run_command,
find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
config = make_config(verilog=True,
generics={
"genstr": "genval",
"genint": 1,
"genbool": True
})
self.assertTrue(
simif.simulate("suite_output_path", "test_suite_name", config))
elaborate_args_file = join("suite_output_path", simif.name,
"irun_elaborate.args")
simulate_args_file = join("suite_output_path", simif.name,
"irun_simulate.args")
run_command.assert_has_calls([
mock.call(
[join("prefix", "irun"), "-f",
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env(),
),
mock.call(
[join("prefix", "irun"), "-f",
basename(simulate_args_file)],
cwd=dirname(simulate_args_file),
env=simif.get_env(),
),
])
for args_file in [elaborate_args_file, simulate_args_file]:
args = read_file(args_file).splitlines()
self.assertIn('-gpg "modulename.genstr => \\"genval\\""', args)
self.assertIn('-gpg "modulename.genint => 1"', args)
self.assertIn('-gpg "modulename.genbool => \\"True\\""', args)
def test_simulate_extra_flags(self, run_command, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
config = make_config(
sim_options={"incisive.irun_sim_flags": ["custom", "flags"]})
self.assertTrue(
simif.simulate("suite_output_path", "test_suite_name", config))
elaborate_args_file = join("suite_output_path", simif.name,
"irun_elaborate.args")
simulate_args_file = join("suite_output_path", simif.name,
"irun_simulate.args")
run_command.assert_has_calls([
mock.call(
[join("prefix", "irun"), "-f",
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env(),
),
mock.call(
[join("prefix", "irun"), "-f",
basename(simulate_args_file)],
cwd=dirname(simulate_args_file),
env=simif.get_env(),
),
])
args = read_file(elaborate_args_file).splitlines()
self.assertIn("custom", args)
self.assertIn("flags", args)
args = read_file(simulate_args_file).splitlines()
self.assertIn("custom", args)
self.assertIn("flags", args)
def test_elaborate(self, run_command, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
config = make_config(verilog=True)
self.assertTrue(
simif.simulate("suite_output_path",
"test_suite_name",
config,
elaborate_only=True))
elaborate_args_file = join("suite_output_path", simif.name,
"irun_elaborate.args")
run_command.assert_has_calls([
mock.call(
[join("prefix", "irun"), "-f",
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env(),
)
])
self.assertEqual(
read_file(elaborate_args_file).splitlines(),
[
"-elaborate",
"-nocopyright",
"-licqueue",
"-errormax 10",
"-nowarn WRMNZD",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-ncerror EVBBOL",
"-ncerror EVBSTR",
"-ncerror EVBNAT",
"-work work",
'-nclibdirname "%s"' % join(self.output_path, "libraries"),
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' %
join("suite_output_path", simif.name, "irun_elaborate.log"),
"-quiet",
"-access +r",
'-input "@run"',
"-top lib.modulename:sv",
],
)
def test_tb_filter_warning_on_runner_cfg_but_not_matching_tb_pattern(
self, tempdir):
design_unit = Entity("entity_ok_but_warning",
file_name=join(tempdir, "file.vhd"))
design_unit.generic_names = ["runner_cfg"]
with mock.patch("vunit.test.bench_list.LOGGER",
autospec=True) as logger:
self.assertTrue(tb_filter(design_unit))
logger.warning.assert_has_calls([
mock.call(
"%s %s has runner_cfg %s but the file name and the %s name does not match regex %s\n"
"in file %s",
"Entity",
"entity_ok_but_warning",
"generic",
"entity",
"^(tb_.*)|(.*_tb)$",
design_unit.file_name,
)
])
def test_tb_filter_warning_on_missing_runner_cfg_when_matching_tb_pattern(
self, tempdir):
design_unit = Module("tb_module_not_ok",
file_name=join(tempdir, "file.vhd"))
design_unit.generic_names = []
with mock.patch("vunit.test.bench_list.LOGGER",
autospec=True) as logger:
self.assertFalse(tb_filter(design_unit))
logger.warning.assert_has_calls([
mock.call(
"%s %s matches testbench name regex %s "
"but has no %s runner_cfg and will therefore not be run.\n"
"in file %s",
"Module",
"tb_module_not_ok",
"^(tb_.*)|(.*_tb)$",
"parameter",
design_unit.file_name,
)
])
def test_compile_source_files_continue_on_error(self):
simif = create_simulator_interface()
project = Project()
project.add_library("lib", "lib_path")
write_file("file1.vhd", "")
file1 = project.add_source_file("file1.vhd", "lib", file_type="vhdl")
write_file("file2.vhd", "")
file2 = project.add_source_file("file2.vhd", "lib", file_type="vhdl")
write_file("file3.vhd", "")
file3 = project.add_source_file("file3.vhd", "lib", file_type="vhdl")
project.add_manual_dependency(file2, depends_on=file1)
def compile_source_file_command(source_file):
"""
Dummy compile command
"""
if source_file == file1:
return ["command1"]
if source_file == file2:
return ["command2"]
if source_file == file3:
return ["command3"]
raise AssertionError
def check_output_side_effect(command, env=None): # pylint: disable=missing-docstring, unused-argument
if command == ["command1"]:
raise subprocess.CalledProcessError(returncode=-1,
cmd=command,
output="bad stuff")
return ""
simif.compile_source_file_command.side_effect = compile_source_file_command
with mock.patch("vunit.sim_if.check_output",
autospec=True) as check_output:
check_output.side_effect = check_output_side_effect
printer = MockPrinter()
self.assertRaises(
CompileError,
simif.compile_source_files,
project,
printer=printer,
continue_on_error=True,
)
self.assertEqual(
printer.output,
"""\
Compiling into lib: file3.vhd passed
Compiling into lib: file1.vhd failed
=== Command used: ===
command1
=== Command output: ===
bad stuff
Compiling into lib: file2.vhd skipped
Compile failed
""",
)
self.assertEqual(len(check_output.mock_calls), 2)
check_output.assert_has_calls(
[
mock.call(["command1"], env=simif.get_env()),
mock.call(["command3"], env=simif.get_env()),
],
any_order=True,
)
self.assertEqual(project.get_files_in_compile_order(incremental=True),
[file1, file2])
def test_simulate_verilog(self, run_command, find_cds_root_irun,
find_cds_root_virtuoso):
find_cds_root_irun.return_value = "cds_root_irun"
find_cds_root_virtuoso.return_value = None
simif = IncisiveInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
with mock.patch("vunit.sim_if.check_output",
autospec=True,
return_value="") as dummy:
simif.compile_project(project)
config = make_config(verilog=True)
self.assertTrue(
simif.simulate("suite_output_path", "test_suite_name", config))
elaborate_args_file = join("suite_output_path", simif.name,
"irun_elaborate.args")
simulate_args_file = join("suite_output_path", simif.name,
"irun_simulate.args")
run_command.assert_has_calls([
mock.call(
[join("prefix", "irun"), "-f",
basename(elaborate_args_file)],
cwd=dirname(elaborate_args_file),
env=simif.get_env(),
),
mock.call(
[join("prefix", "irun"), "-f",
basename(simulate_args_file)],
cwd=dirname(simulate_args_file),
env=simif.get_env(),
),
])
self.assertEqual(
read_file(elaborate_args_file).splitlines(),
[
"-elaborate",
"-nocopyright",
"-licqueue",
"-errormax 10",
"-nowarn WRMNZD",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-ncerror EVBBOL",
"-ncerror EVBSTR",
"-ncerror EVBNAT",
"-work work",
'-nclibdirname "%s"' % join(self.output_path, "libraries"),
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' %
join("suite_output_path", simif.name, "irun_elaborate.log"),
"-quiet",
'-reflib "lib_path"',
"-access +r",
'-input "@run"',
"-top lib.modulename:sv",
],
)
self.assertEqual(
read_file(simulate_args_file).splitlines(),
[
"-nocopyright",
"-licqueue",
"-errormax 10",
"-nowarn WRMNZD",
"-nowarn DLCPTH",
"-nowarn DLCVAR",
"-ncerror EVBBOL",
"-ncerror EVBSTR",
"-ncerror EVBNAT",
"-work work",
'-nclibdirname "%s"' % join(self.output_path, "libraries"),
'-cdslib "%s"' % join(self.output_path, "cds.lib"),
'-log "%s"' %
join("suite_output_path", simif.name, "irun_simulate.log"),
"-quiet",
'-reflib "lib_path"',
"-access +r",
'-input "@run"',
"-top lib.modulename:sv",
],
)