def Rotate_r(num1, num_bits): if num_bits > 8: # limits the number of cycles num_bits = 8 OP.SEC(num1 & 0b1) for x in range(0, num_bits): OP.LDA(num1) OP.ROR() num1 = OP.STA() OP.SEC(ALU.read_C_OUT()) return(num1, ALU.read_C_OUT()) # shift l, rotate r, rotate l
def Add(num1, num2):
# Split the two 16 bit input numbers into four 8 bit integers
num1lo = extract_byte(num1, 'low')
num1hi = extract_byte(num1, 'high')
num2lo = extract_byte(num2, 'low')
num2hi = extract_byte(num2, 'high')
if globals.debug == True:
print("num1lo: " , num1lo)
print("num1hi: " , num1hi << 8)
print("num2lo: " , num2lo)
print("num2hi: " , num2hi << 8)
# 6502 Assembly for 16 bit addition
OP.CLC() # clear the carry in
OP.LDA(num1lo)
cout = OP.ADC(num2lo)
reslo = OP.STA() # store sum of LSBs
if globals.debug == True:
print("cout1: " , cout)
ALU.set_C_IN(cout)
OP.LDA(num1hi)
OP.ADC(num2hi) # add the MSBs using the carry from above
reshi = OP.STA() # store sum of MSBs
cout = ALU.read_C_OUT()
# Debug
if globals.debug == True:
print("cout: " , cout)
print("reslo: " , reslo)
print("reshi: " , reshi)
# Return result
return((cout << 16) + (reshi << 8) + reslo)
def counter_test():
numA = 1
numB = 1
while numB < 256:
write_register(numA, numB)
RegADD.clock_data()
result = RegADD.read_register() + (ALU.read_C_OUT() << 8)
print(numA, " +", numB, " = ", result)
if result != (numA + numB):
print("NumA: ", numA)
print("Numb: ", numB)
print("NumA: ", result)
break
numB += 1
time.sleep(delayTime)
def ADC(addend): # ADd with Carry # Write to register A RegA.write_register(addend) # Activate Adder Output ALU.unset_all() ALU.set_ADD(1) # Read result C_OUT = ALU.read_C_OUT() RegADD.clock_data() SUM = RegADD.read_register() # Store result in Accumulator LDA(SUM) return(C_OUT)
def AND(num): # bitwise AND with accumulator # Write to register A RegA.write_register(num) # Activate AND output ALU.unset_all() ALU.set_AND(1) # Read result C_OUT = ALU.read_C_OUT() RegADD.clock_data() AND = RegADD.read_register() # Store result in Accumulator LDA(AND) return(C_OUT)
def SBC(subtrahend): # SuBtract with Carry # Locally store Accumulator minuend = STA() # Invert the subtrahend # RegB.write_inverted_register(subtrahend) RegB.write_inverted_register(subtrahend) # Add 1 to the inverted subtrahend. Result is 2's complement ADC(1) twos_comp = STA() # Add the result of step 2 to the minuend LDA(minuend) ADC(twos_comp) C_OUT = ALU.read_C_OUT() return(C_OUT)
def BCC(): # Branch on Carry Clear carry = ALU.read_C_OUT() if carry == 0: return(True) else: return(False)
