#------------------------------------------------------------------------------
# make HSPICE directory tree
#------------------------------------------------------------------------------
hspice = 1
finesim = 0
preparations.dir_tree(outMode, absPvtDir_plat, outputDir, extDir,
calibreRulesDir, hspiceDir, finesimDir, dco_flowDir,
outbuff_div_flowDir, pll_flowDir, platform)
dco_CC_name, dco_FC_name = preparations.aux_copy_export(
dco_flowDir, dco_CC_lib, dco_FC_lib)
#------------------------------------------------------------------------------
# design & test_env sets definition
#------------------------------------------------------------------------------
sys.setrecursionlimit(10000) #expand the recursion limit if exceeded
vm1 = txt_mds.varmap()
#vm1.get_var('n_cc',24,28,4) #[0]=n_cc
#vm1.get_var('n_drv',5,5,1) #[1]=n_drv
#vm1.get_var('n_fc',40,48,8) #[2]=n_fc
#vm1.get_var('n_stg',3,5,2) #[3]=n_stg
# 5stg only
vm1.get_var('n_cc', 24, 28, 4) #[0]=n_cc
vm1.get_var('n_drv', 5, 5, 1) #[1]=n_drv
vm1.get_var('n_fc', 40, 48, 8) #[2]=n_fc
vm1.get_var('n_stg', 5, 5, 1) #[3]=n_stg
# design solution
##vm1.get_var('n_cc',70,70,1) #[0]=n_cc
#vm1.get_var('n_cc',24,24,1) #[0]=n_cc: debug purpose
#vm1.get_var('n_drv',28,28,1) #[1]=n_drv
def gen_tb_wrapped(hspiceModel, tb_dir, format_dir, ncell, ndrv, nfc, nstg,
vdd, temp, fc_en_type, sim_time, corner_lib, designName,
netlistDir):
#=====================================================
# model constants for trans simulation time calculation
#=====================================================
if len(vdd) > 1 and len(temp) > 1:
vdd_min, vdd_max = txt_mds.mM(vdd) #generate function of minMax step
vdd.remove(vdd_min)
temp_min, temp_max = txt_mds.mM(temp)
temp.remove(temp_min)
elif len(vdd) == 1 and len(temp) == 1:
vdd_min = vdd[0]
vdd_max = vdd[0]
temp_min = temp[0]
temp_max = temp[0]
r_file = open(format_dir + "form_tb_ring_osc.sp", "r")
lines = list(r_file.readlines())
#===============================================
# writing
#===============================================
L_lines = []
L_flag = 0
netmap1 = txt_mds.netmap() #35
netmap1.get_net('Ti', None, sim_time, sim_time, 1)
netmap1.get_net('TE', None, sim_time, sim_time, 1)
netmap1.get_net('vd', None, vdd[0], vdd[0], 1)
netmap1.get_net('ND', netlistDir, None, None, 1)
netmap1.get_net('dn', 'wrapped_' + designName, None, None, 1)
#----- only string -----------
netmap1.get_net('hm', hspiceModel, None, None, None)
netmap1.get_net('cr', corner_lib, None, None, None)
#===============================================
# number of control node definition for v2
#===============================================
N_ctrl_fc = nstg * nfc
N_ctrl_cc = nstg * ncell
#===============================================
# generate variable maps: FCWs to sweep
# (CC,FC)=(0,0),(0,Nfc),(1,0),(Ncc//2,0)
# (Ncc//2,Nfc//2),(Ncc//2,Nfc)
# (Ncc,Nfc)
#===============================================
vm2 = txt_mds.varmap()
vm2.get_var(
'vdd', vdd[0], vdd[0],
1) #vm2.comblist[0]=vdd #???? why like this? because of get_var
if len(vdd) > 1:
for i in range(1, len(vdd)):
vm2.add_val('vdd', vdd[i], vdd[i], 1)
vm2.get_var('temp', temp[0], temp[0], 1) #vm2.comblist[1]=temp
if len(temp) > 1:
for i in range(1, len(temp)):
vm2.add_val('temp', temp[i], temp[i], 1)
vm2.cal_nbigcy()
vm2.combinate() #vdd/temp combination
var_list = [[[] for x in range(7)]
for y in range(len(vm2.comblist[0]) - 1)]
if fc_en_type == 1:
for i in range(1, len(vm2.comblist[0])):
var_list[i - 1][0] = [0, 0, vm2.comblist[0][i], vm2.comblist[1][i]]
var_list[i - 1][1] = [
0, N_ctrl_fc, vm2.comblist[0][i], vm2.comblist[1][i]
]
var_list[i - 1][2] = [1, 0, vm2.comblist[0][i], vm2.comblist[1][i]]
var_list[i - 1][3] = [
N_ctrl_cc // 2, 0, vm2.comblist[0][i], vm2.comblist[1][i]
]
var_list[i - 1][4] = [
N_ctrl_cc // 2, N_ctrl_fc // 2, vm2.comblist[0][i],
vm2.comblist[1][i]
]
var_list[i - 1][5] = [
N_ctrl_cc // 2, N_ctrl_fc, vm2.comblist[0][i],
vm2.comblist[1][i]
]
var_list[i - 1][6] = [
N_ctrl_cc, N_ctrl_fc, vm2.comblist[0][i], vm2.comblist[1][i]
]
else:
for i in range(1, len(vm2.comblist[0])):
var_list[i - 1][0] = [
0, N_ctrl_fc, vm2.comblist[0][i], vm2.comblist[1][i]
]
var_list[i - 1][1] = [0, 0, vm2.comblist[0][i], vm2.comblist[1][i]]
var_list[i - 1][2] = [
1, N_ctrl_fc, vm2.comblist[0][i], vm2.comblist[1][i]
]
var_list[i - 1][3] = [
N_ctrl_cc // 2, N_ctrl_fc, vm2.comblist[0][i],
vm2.comblist[1][i]
]
var_list[i - 1][4] = [
N_ctrl_cc // 2, N_ctrl_fc // 2, vm2.comblist[0][i],
vm2.comblist[1][i]
]
var_list[i - 1][5] = [
N_ctrl_cc // 2, 0, vm2.comblist[0][i], vm2.comblist[1][i]
]
var_list[i - 1][6] = [
N_ctrl_cc, 0, vm2.comblist[0][i], vm2.comblist[1][i]
]
#===================================================================
# DATA table gen for parametric sweep
#===================================================================
#----- lateral stuffs: names --------
netmap1.get_net('vf', 'vf', 0, N_ctrl_fc - 1, 1) #for v2
netmap1.get_net('vc', 'vc', 0, N_ctrl_cc - 1, 1) #for v2
#----- lateral stuffs: FCW values --------
#with open(tb_dir+"tb_%dring%d_osc%d_FC%d.sp"%(ndrv,ncell,nstg,nfc),"w") as w_file:
with open(tb_dir + "tb_" + designName + ".sp", "w") as w_file:
for line in lines:
if line[0:4] == '@L@W':
line = line[2:len(line) - 1]
for ivt in range(len(var_list)):
for ifcw in range(len(var_list[0])):
netmap2 = txt_mds.netmap()
netmap2.get_net('f1', None, 'd2o', N_ctrl_fc,
var_list[ivt][ifcw][1])
netmap2.get_net('c1', None, 'd2o', N_ctrl_cc,
var_list[ivt][ifcw][0])
netmap2.get_net('vd', None, var_list[ivt][ifcw][2],
var_list[ivt][ifcw][2], 1)
netmap2.get_net('tm', None, var_list[ivt][ifcw][3],
var_list[ivt][ifcw][3], 1)
netmap2.printline(line, w_file)
w_file.write('\n')
else:
netmap1.printline(line, w_file)
def gen_tb_pex(CF, Cc, Cf, PDK, finesim, tb_dir, format_dir, ncell, ndrv, nfc,
nstg_start, nstg_end, nstg_step, vdd, temp, nper, design_name,
sav):
#=====================================================
# model constants for trans simulation time calculation
#=====================================================
CB = Cc * (ndrv + ncell) + Cf * nfc
vm1 = txt_mds.varmap() ###modify here!!
vm1.get_var('ncell', ncell, ncell, 1)
vm1.get_var('nstage', nstg_start, nstg_end,
nstg_step) #vm1.comblist[1]=nstg
vm1.get_var('ndrive', ndrv, ndrv, 1)
vm1.cal_nbigcy()
vm1.combinate()
num_var = 1
nstg_swp = nstg_end - nstg_start + 1
N_recur = 5 * 3 * len(vdd) * len(temp) * 4
# sys.setrecursionlimit(N_recur+1) #expand the recursion limit if exceeded
if len(vdd) > 1 and len(temp) > 1:
vdd_min, vdd_max = txt_mds.mM(vdd) #generate function of minMax step
vdd.remove(vdd_min)
temp_min, temp_max = txt_mds.mM(temp)
temp.remove(temp_min)
elif len(vdd) == 1 and len(temp) == 1:
vdd_min = vdd[0]
vdd_max = vdd[0]
temp_min = temp[0]
temp_max = temp[0]
#r_file=open("./tb_ring_osc_FC.sp","r")
if finesim == 0:
if sav == 0:
r_file = open(format_dir + "form_pex_tb_ring_osc.sp", "r")
else:
r_file = open(format_dir + "form_pex_tb_ring_osc_sav.sp", "r")
elif finesim == 1:
r_file = open(format_dir + "form_fs_pex_tb_ring_osc.sp", "r")
lines = list(r_file.readlines())
for i in range(1, len(vm1.comblist[0])):
#===============================================
# transient sim time calculation
#===============================================
Fmin_mdl = 1 / (CB + nfc * CF) * (ndrv) / vm1.comblist[1][i]
print('estimated Fmin=%e' % (Fmin_mdl))
#per_max_mdl=vm1.comblist[1][i]*(CB+nfc*CF)/ndrv
per_max_mdl = 1 / Fmin_mdl
print('estimated sim_time=%e' % (per_max_mdl * 25))
TD = 00e-9
#===============================================
# writing
#===============================================
L_lines = []
L_flag = 0
netmap1 = txt_mds.netmap() #35
netmap1.get_net('Ti', None, TD + per_max_mdl * 25,
TD + per_max_mdl * 25, 1)
netmap1.get_net('TE', None, TD + per_max_mdl * (25 + nper),
TD + per_max_mdl * (25 + nper), 1)
netmap1.get_net('vd', None, vdd[0], vdd[0], 1)
netmap1.get_net('DN', design_name, None, None, None)
#----- only string -----------
netmap1.get_net('PK', PDK, None, None, None)
#===============================================
# number of control node definition for v2
#===============================================
N_ctrl_fc = vm1.comblist[1][i] * nfc
N_ctrl_cc = vm1.comblist[1][i] * ncell
#===============================================
# generate variable maps: FCWs to sweep
# (CC,FC)=(0,0),(0,Nfc),(1,0),(Ncc//2,0)
# (Ncc//2,Nfc//2),(Ncc//2,Nfc)
# (Ncc,Nfc)
#===============================================
vm2 = txt_mds.varmap()
vm2.get_var(
'vdd', vdd[0], vdd[0],
1) #vm2.comblist[0]=vdd #???? why like this? because of get_var
if len(vdd) > 1:
for i in range(1, len(vdd)):
vm2.add_val('vdd', vdd[i], vdd[i], 1)
vm2.get_var('temp', temp[0], temp[0], 1) #vm2.comblist[1]=temp
if len(temp) > 1:
for i in range(1, len(temp)):
vm2.add_val('temp', temp[i], temp[i], 1)
vm2.cal_nbigcy()
vm2.combinate() #vdd/temp combination
var_list = [[[] for x in range(7)]
for y in range(len(vm2.comblist[0]) - 1)]
for i in range(1, len(vm2.comblist[0])):
var_list[i - 1][0] = [0, 0, vm2.comblist[0][i], vm2.comblist[1][i]]
var_list[i - 1][1] = [
0, N_ctrl_fc, vm2.comblist[0][i], vm2.comblist[1][i]
]
var_list[i - 1][2] = [1, 0, vm2.comblist[0][i], vm2.comblist[1][i]]
var_list[i - 1][3] = [
N_ctrl_cc // 2, 0, vm2.comblist[0][i], vm2.comblist[1][i]
]
var_list[i - 1][4] = [
N_ctrl_cc // 2, N_ctrl_fc // 2, vm2.comblist[0][i],
vm2.comblist[1][i]
]
var_list[i - 1][5] = [
N_ctrl_cc // 2, N_ctrl_fc, vm2.comblist[0][i],
vm2.comblist[1][i]
]
var_list[i - 1][6] = [
N_ctrl_cc, N_ctrl_fc, vm2.comblist[0][i], vm2.comblist[1][i]
]
#===================================================================
# DATA table gen for parametric sweep
#===================================================================
#----- lateral stuffs: names --------
netmap1.get_net('vf', 'vf', 0, N_ctrl_fc - 1, 1) #for v2
netmap1.get_net('vc', 'vc', 0, N_ctrl_cc - 1, 1) #for v2
#----- lateral stuffs: FCW values --------
with open(tb_dir + "tb_" + design_name + ".sp", "w") as w_file:
for line in lines:
if line[0:4] == '@L@W':
line = line[2:len(line) - 1]
for ivt in range(len(var_list)):
for ifcw in range(len(var_list[0])):
netmap2 = txt_mds.netmap()
netmap2.get_net('f1', None, 'd2o', N_ctrl_fc,
var_list[ivt][ifcw][1])
netmap2.get_net('c1', None, 'd2o', N_ctrl_cc,
var_list[ivt][ifcw][0])
netmap2.get_net('vd', None, var_list[ivt][ifcw][2],
var_list[ivt][ifcw][2], 1)
netmap2.get_net('tm', None, var_list[ivt][ifcw][3],
var_list[ivt][ifcw][3], 1)
netmap2.printline(line, w_file)
w_file.write('\n')
#for j in range(1,len(vm2.comblist[0])):
## print('one line')
# #print vm2.comblist[0][j]
# netmap2=txt_mds.netmap()
# #netmap2.get_net('f1',None,'d2o',nfc,vm2.comblist[0][j])
# netmap2.get_net('f1',None,'d2o',N_ctrl_fc,vm2.comblist[0][j])
# netmap2.get_net('c1',None,'d2o',N_ctrl_cc,vm2.comblist[1][j])
# netmap2.get_net('vd',None,vm2.comblist[2][j],vm2.comblist[2][j],1)
# netmap2.get_net('tm',None,vm2.comblist[3][j],vm2.comblist[3][j],1)
# netmap2.printline(line,w_file)
# w_file.write('\n')
else:
netmap1.printline(line, w_file)
def gen_netlist(netlist_dir, format_dir, ncell, ndrv, nfc, nstg_start,
nstg_end, nstg_step, wellpin, designName):
vm1 = txt_mds.varmap()
vm1.get_var('ncell', ncell, ncell, 1)
vm1.get_var('nstage', nstg_start, nstg_end, nstg_step)
vm1.get_var('ndrv', ndrv, ndrv, 1)
vm1.cal_nbigcy()
vm1.combinate()
for i in range(1, len(vm1.comblist[0])):
if wellpin == 0:
r_netlist = open(format_dir + "form_ring_osc.sp", "r")
else:
r_netlist = open(format_dir + "form_ring_osc_wellpin.sp", "r")
lines = list(r_netlist.readlines())
nstg = vm1.comblist[1][i]
#print ("ntlst nstg=%d"%(nstg))
npar = vm1.comblist[0][i]
ndrv = vm1.comblist[2][i]
netmap1 = txt_mds.netmap()
### enable voltages for CC,FC ###
netmap1.get_net('vf', None, 0, nstg - 1, 1)
netmap1.get_net('nf', None, 0, nstg - 1, 1)
#netmap1.get_net('Vf','vf',None,0,nstg)
netmap1.get_net('Vf', 'vf', 0, nstg - 1, 1) #for v2
netmap1.get_net('vc', None, 0, nstg - 1, 1)
netmap1.get_net('nc', None, 0, nstg - 1, 1)
#netmap1.get_net('Vc','vc',None,0,nstg)
netmap1.get_net('Vc', 'vc', 0, nstg - 1, 1) #for v2
###driver before last
netmap1.get_net('id', None, 1, nstg - 1, 1)
netmap1.get_net('Dn', 'n', 1, nstg - 1, 1)
netmap1.get_net('Dp', 'p', 1, nstg - 1, 1)
netmap1.get_net('dp', 'p', 2, nstg, 1)
netmap1.get_net('dn', 'n', 2, nstg, 1)
###driver last
netmap1.get_net('iD', None, nstg - 1, nstg - 1, 1)
netmap1.get_net('DN', 'n', nstg, nstg, 1)
netmap1.get_net('DP', 'p', nstg, nstg, 1)
if nstg % 2 == 1:
netmap1.get_net('dP', 'p', 1, 1, 1)
netmap1.get_net('dN', 'n', 1, 1, 1)
if nstg % 2 == 0:
netmap1.get_net('dP', 'n', 1, 1, 1)
netmap1.get_net('dN', 'p', 1, 1, 1)
###CC before last
netmap1.get_net('ic', None, 1, nstg - 1, 1)
netmap1.get_net('ni', None, 0, nstg - 2, 1)
netmap1.get_net('In', 'n', 1, nstg - 1, 1)
netmap1.get_net('Ip', 'p', 1, nstg - 1, 1)
netmap1.get_net('Op', 'p', 2, nstg, 1)
netmap1.get_net('On', 'n', 2, nstg, 1)
###CC last
netmap1.get_net('IC', None, nstg - 1, nstg - 1, 1)
netmap1.get_net('NI', None, nstg - 1, nstg - 1, 1)
netmap1.get_net('IN', 'n', nstg, nstg, 1)
netmap1.get_net('IP', 'p', nstg, nstg, 1)
if nstg % 2 == 1:
netmap1.get_net('OP', 'p', 1, 1, 1)
netmap1.get_net('ON', 'n', 1, 1, 1)
if nstg % 2 == 0:
netmap1.get_net('OP', 'n', 1, 1, 1)
netmap1.get_net('ON', 'p', 1, 1, 1)
#-----------FC-----------------
netmap1.get_net('if', None, 0, nstg - 1, 1)
netmap1.get_net('fn', None, 0, nstg - 1, 1)
netmap1.get_net('in', 'n', 1, nstg, 1)
netmap1.get_net('ip', 'p', 1, nstg, 1)
#-----------adding for parallel drv------
for ip in range(1, ndrv):
netmap1.add_val('id', None, 1 + ip * nstg, (ip + 1) * nstg - 1, 1)
netmap1.add_val('Dn', 'n', 1, nstg - 1, 1)
netmap1.add_val('Dp', 'n', 1, nstg - 1, 1)
netmap1.add_val('dp', 'n', 2, nstg, 1)
netmap1.add_val('dn', 'n', 2, nstg, 1)
netmap1.add_val('iD', None, (ip + 1) * nstg - 1,
(ip + 1) * nstg - 1, 1)
netmap1.add_val('DN', 'n', nstg, nstg, 1)
netmap1.add_val('DP', 'p', nstg, nstg, 1)
if nstg % 2 == 1:
netmap1.add_val('dP', 'p', 1, 1, 1)
netmap1.add_val('dN', 'n', 1, 1, 1)
if nstg % 2 == 0:
netmap1.add_val('dP', 'n', 1, 1, 1)
netmap1.add_val('dN', 'p', 1, 1, 1)
#-----------adding for parallel CC------
for ip in range(1, npar):
#--------control voltages for CC----------
netmap1.add_val('vc', None, ip * nstg, (ip + 1) * nstg - 1, 1)
netmap1.add_val('nc', None, ip * nstg, (ip + 1) * nstg - 1, 1)
#netmap1.add_val('Vc','vc',None,ip,nstg)
netmap1.add_val('Vc', 'vc', ip * nstg, (ip + 1) * nstg - 1, 1)
#--------CC cells----------
netmap1.add_val('ic', None, 1 + ip * nstg, (ip + 1) * nstg - 1, 1)
netmap1.add_val('ni', None, ip * nstg, (ip + 1) * nstg - 2, 1)
netmap1.add_val('In', 'n', 1, nstg - 1, 1)
netmap1.add_val('Ip', 'n', 1, nstg - 1, 1)
netmap1.add_val('On', 'n', 2, nstg, 1)
netmap1.add_val('Op', 'n', 2, nstg, 1)
#--------CC last------------
netmap1.add_val('IC', None, (ip + 1) * nstg - 1,
(ip + 1) * nstg - 1, 1)
netmap1.add_val('NI', None, (ip + 1) * nstg - 1,
(ip + 1) * nstg - 1, 1)
netmap1.add_val('IN', 'n', nstg, nstg, 1)
netmap1.add_val('IP', 'p', nstg, nstg, 1)
if nstg % 2 == 1:
netmap1.add_val('OP', 'p', 1, 1, 1)
netmap1.add_val('ON', 'n', 1, 1, 1)
if nstg % 2 == 0:
netmap1.add_val('OP', 'n', 1, 1, 1)
netmap1.add_val('ON', 'p', 1, 1, 1)
#-----------add parallel FC-------------
for ip in range(1, nfc):
#----------control voltages for FC--------
netmap1.add_val('vf', None, ip * nstg, (ip + 1) * nstg - 1, 1)
netmap1.add_val('nf', None, ip * nstg, (ip + 1) * nstg - 1, 1)
#netmap1.add_val('Vf','vf',None,ip,nstg)
netmap1.add_val('Vf', 'vf', ip * nstg, (ip + 1) * nstg - 1,
1) #for v2
#----------FC cells---------------
netmap1.add_val('if', None, ip * nstg, (ip + 1) * nstg - 1, 1)
netmap1.add_val('fn', None, ip * nstg, (ip + 1) * nstg - 1, 1)
netmap1.add_val('in', 'n', 1, nstg, 1)
netmap1.add_val('ip', 'p', 1, nstg, 1)
with open(netlist_dir + designName + ".sp", "w") as w_netlist:
for line in lines:
netmap1.printline(line, w_netlist)