def unaryOps_v(name,
Not,
Invert,
UnaryAdd,
UnarySub,
arg):
return setupCosimulation(**locals())
def binaryOps_v(
name,
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
LeftShift,
## Mod,
Mul,
## Pow,
RightShift,
Sub,
Sum,
Sum1,
Sum2,
Sum3,
EQ,
NE,
LT,
GT,
LE,
GE,
And,
Or,
left,
right,
bit):
return setupCosimulation(**locals())
def multiOps_v( name,
Bitand,
Bitor,
Bitxor,
And,
Or,
argm, argn, argp):
return setupCosimulation(**locals())
def top(name, count, enable, clock, reset, n, arch="myhdl"):
if arch == "verilog":
return setupCosimulation(**locals())
if path.exists(objfile):
os.remove(objfile)
os.system(analyze_cmd)
return Cosimulation(simulate_cmd, **locals())
else:
inc_initial_inst = inc_initial(count, enable, clock, reset, n)
return inc_initial_inst
def top(name, count, enable, clock, reset, n, arch="myhdl"):
if arch == "verilog":
return setupCosimulation(**locals())
if path.exists(objfile):
os.remove(objfile)
os.system(analyze_cmd)
return Cosimulation(simulate_cmd, **locals())
else:
inc_initial_inst = inc_initial(count, enable, clock, reset, n)
return inc_initial_inst
def augmOps_v( name,
Bitand,
Bitor,
Bitxor,
FloorDiv,
LeftShift,
Mod,
Mul,
RightShift,
Sub,
Sum,
left, right):
return setupCosimulation(**locals())
def augmOps_v(
name,
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
LeftShift,
## Mod,
Mul,
RightShift,
Sub,
Sum,
left,
right):
return setupCosimulation(**locals())
def binaryOps_v(name,
Bitand,
Bitor,
Bitxor,
FloorDiv,
LeftShift,
Mod,
Mul,
Pow,
RightShift,
Sub,
Sum,
EQ,
NE,
LT,
GT,
LE,
GE,
And,
Or,
left, right):
return setupCosimulation(**locals())
def binaryOps_v(name,
## Bitand,
## Bitor,
## Bitxor,
## FloorDiv,
LeftShift,
## Mod,
Mul,
## Pow,
RightShift,
Sub,
Sum, Sum1, Sum2, Sum3,
EQ,
NE,
LT,
GT,
LE,
GE,
And,
Or,
left, right, bit):
return setupCosimulation(**locals())
def bench(self, obuf=None):
if obuf:
toVerilog(tristate_obuf_i, obuf)
A, Y, OE = obuf.interface()
else:
Y = TristateSignal(True)
A = Signal(True)
OE = Signal(False)
toVerilog(tristate_obuf, A, Y, OE)
inst = setupCosimulation(name='tristate_obuf', **toVerilog.portmap)
#inst = tristate_obuf(A, Y, OE)
@instance
def stimulus():
yield delay(1)
#print now(), A, OE, Y
self.assertEqual(Y, None)
OE.next = True
yield delay(1)
#print now(), A, OE, Y
self.assertEqual(Y, A)
A.next = not A
yield delay(1)
#print now(), A, OE, Y
self.assertEqual(Y, A)
OE.next = False
yield delay(1)
#print now(), A, OE, Y
self.assertEqual(Y, None)
raise StopSimulation
return instances()
def bench(self, obuf=None):
if obuf:
toVerilog(tristate_obuf_i, obuf)
A, Y, OE = obuf.interface()
else:
Y = TristateSignal(True)
A = Signal(True)
OE = Signal(False)
toVerilog(tristate_obuf, A, Y, OE)
inst = setupCosimulation(name='tristate_obuf', **toVerilog.portmap)
#inst = tristate_obuf(A, Y, OE)
@instance
def stimulus():
yield delay(1)
#print now(), A, OE, Y
self.assertEqual(Y, None)
OE.next = True
yield delay(1)
#print now(), A, OE, Y
self.assertEqual(Y, A)
A.next = not A
yield delay(1)
#print now(), A, OE, Y
self.assertEqual(Y, A)
OE.next = False
yield delay(1)
#print now(), A, OE, Y
self.assertEqual(Y, None)
raise StopSimulation
return instances()
def GrayIncReg_v(name, graycnt, enable, clock, reset, width):
return setupCosimulation(**locals())
def Infertest_v(name, a, out):
return setupCosimulation(**locals())
def ConstWire_v(name, p, q):
return setupCosimulation(**locals())
def multiOps_v(name, Bitand, Bitor, Bitxor, And, Or, argm, argn, argp):
return setupCosimulation(**locals())
def design_v(name, a, b, c, d, p, q, r):
return setupCosimulation(**locals())
def expressions_v(a, b, clk):
return setupCosimulation(**locals())
def unaryOps_v(name, Not, Invert, UnaryAdd, UnarySub, arg):
return setupCosimulation(**locals())
def expressions_v(a, b, clk): return setupCosimulation(**locals())
def HecCalculator_v(name, hec, header):
return setupCosimulation(**locals())
def FramerCtrl_v(name, SOF, state, syncFlag, clk, reset_n):
return setupCosimulation(**locals())
def design_v(name, a, b, c, d, p, q, r):
return setupCosimulation(**locals())
def HecCalculator_v(name, hec, header):
return setupCosimulation(**locals())
def binaryOps_v(name, Bitand, Bitor, Bitxor, FloorDiv, LeftShift, Mod, Mul,
Pow, RightShift, Sub, Sum, EQ, NE, LT, GT, LE, GE, And, Or,
left, right):
return setupCosimulation(**locals())
def Infertest_v(name, a, out):
return setupCosimulation(**locals())
def RandomScrambler_v(name,
o7, o6, o5, o4, o3, o2, o1, o0,
i7, i6, i5, i4, i3, i2, i1, i0):
return setupCosimulation(**locals())
def edge_v(name, flag, sig, clock):
return setupCosimulation(**locals())
def GrayIncReg_v(name, graycnt, enable, clock, reset, width):
return setupCosimulation(**locals())
def beh_v(name, count, enable, clock, reset):
return setupCosimulation(**locals())
def rom_v(name, dout, addr, clk):
return setupCosimulation(**locals())
def ConstWire_v(name, p, q):
return setupCosimulation(**locals())
def bin2gray_v(name, B, G):
return setupCosimulation(**locals())
def FramerCtrl_v(name, SOF, state, syncFlag, clk, reset_n):
return setupCosimulation(**locals())
def beh_v(name, count, enable, clock, reset):
return setupCosimulation(**locals())
def LoopTest_v(name, a, out):
return setupCosimulation(**locals())
def LoopTest_v(name, a, out):
return setupCosimulation(**locals())
def Ignorecode_v(name, a, b, c):
return setupCosimulation(**locals())
def bin2gray_v(name, B, G):
return setupCosimulation(**locals())
def ram_v(name, dout, din, addr, we, clk, depth=4):
return setupCosimulation(**locals())
def ram_v(name, dout, din, addr, we, clk, depth=4):
return setupCosimulation(**locals())
def Ignorecode_v(name, a, b, c):
return setupCosimulation(**locals())
def RandomScrambler_v(name,
o7, o6, o5, o4, o3, o2, o1, o0,
i7, i6, i5, i4, i3, i2, i1, i0):
return setupCosimulation(**locals())
def rom_v(name, dout, addr, clk):
return setupCosimulation(**locals())
