def test(): width = 8 x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)] toVerilog(TestModule, x,a,b,c,d,e) verilogCompile(TestModule.__name__)
def test(): clk = Signal(bool(0)) reset_n = Signal(bool(1)) SOF = Signal(bool(0)) toVerilog(top, SOF, clk, reset_n) verilogCompile(top.func_name)
def test(): clk = Signal(bool(0)) reset_n = Signal(bool(1)) SOF = Signal(bool(0)) toVerilog(top, SOF, clk, reset_n) verilogCompile(top.__name__)