def __init__(self,
sys_clk_freq=int(100e6),
with_pwm=False,
with_gpio=False,
gpio_width=32,
with_spi_master=False,
spi_master_data_width=8,
spi_master_clk_freq=8e6,
**kwargs):
platform = Platform(_io)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform)
# SoCMini ----------------------------------------------------------------------------------
print(kwargs)
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf,
debug=False)
self.add_csr("usb")
# Wishbone Master
if kwargs["bus"] == "wishbone":
wb_bus = wishbone.Interface()
self.bus.add_master(master=wb_bus)
platform.add_extension(wb_bus.get_ios("wb"))
wb_pads = platform.request("wb")
self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
# IRQs
for name, loc in sorted(self.irq.locs.items()):
module = getattr(self, name)
platform.add_extension([("irq_" + name, 0, Pins(1))])
irq_pin = platform.request("irq_" + name)
self.comb += irq_pin.eq(module.ev.irq)
def __init__(self, platform, boot_source="rand",
debug=None, bios_file=None,
use_dsp=False, placer="heap", output_dir="build",
pnr_seed=0,
warmboot_offsets=None,
**kwargs):
# Disable integrated RAM as we'll add it later
self.integrated_sram_size = 0
self.output_dir = output_dir
clk_freq = int(12e6)
self.submodules.crg = _CRG(platform)
SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, with_uart=False, **kwargs)
usb_debug = False
if debug is not None:
if debug == "uart":
from litex.soc.cores.uart import UARTWishboneBridge
self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
elif debug == "usb":
usb_debug = True
elif debug == "spi":
import spibone
# Add SPI Wishbone bridge
debug_device = [
("spidebug", 0,
Subsignal("mosi", Pins("dbg:0")),
Subsignal("miso", Pins("dbg:1")),
Subsignal("clk", Pins("dbg:2")),
Subsignal("cs_n", Pins("dbg:3")),
)
]
platform.add_extension(debug_device)
spi_pads = platform.request("spidebug")
self.submodules.spibone = ClockDomainsRenamer("usb_12")(spibone.SpiWishboneBridge(spi_pads, wires=4))
self.add_wb_master(self.spibone.wishbone)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.use_external_variant("rtl/VexRiscv_Fomu_Debug.v")
os.path.join(output_dir, "gateware")
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
else:
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.use_external_variant("rtl/VexRiscv_Fomu.v")
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
# free up scarce block RAM.
spram_size = 128*1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
# Add a Messible for device->host communications
self.submodules.messible = Messible()
if boot_source == "rand":
kwargs['cpu_reset_address'] = 0
bios_size = 0x2000
self.submodules.random_rom = RandomFirmwareROM(bios_size)
self.add_constant("ROM_DISABLE", 1)
self.register_rom(self.random_rom.bus, bios_size)
elif boot_source == "bios":
kwargs['cpu_reset_address'] = 0
if bios_file is None:
self.integrated_rom_size = bios_size = 0x2000
self.submodules.rom = wishbone.SRAM(bios_size, read_only=True, init=[])
self.register_rom(self.rom.bus, bios_size)
else:
bios_size = 0x2000
self.submodules.firmware_rom = FirmwareROM(bios_size, bios_file)
self.add_constant("ROM_DISABLE", 1)
self.register_rom(self.firmware_rom.bus, bios_size)
elif boot_source == "spi":
kwargs['cpu_reset_address'] = 0
self.integrated_rom_size = bios_size = 0x2000
gateware_size = 0x1a000
self.flash_boot_address = self.mem_map["spiflash"] + gateware_size
self.submodules.rom = wishbone.SRAM(bios_size, read_only=True, init=[])
self.register_rom(self.rom.bus, bios_size)
else:
raise ValueError("unrecognized boot_source: {}".format(boot_source))
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads, dummy=platform.spi_dummy, endianness="little")
self.register_mem("spiflash", self.mem_map["spiflash"], self.lxspi.bus, size=platform.spi_size)
# Add USB pads, as well as the appropriate USB controller. If no CPU is
# present, use the DummyUsb controller.
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf, debug=usb_debug)
else:
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_debug)
if usb_debug:
self.add_wb_master(self.usb.debug_bridge.wishbone)
# For the EVT board, ensure the pulldown pin is tristated as an input
if hasattr(usb_pads, "pulldown"):
pulldown = TSTriple()
self.specials += pulldown.get_tristate(usb_pads.pulldown)
self.comb += pulldown.oe.eq(0)
# Add GPIO pads for the touch buttons
platform.add_extension(TouchPads.touch_device)
self.submodules.touch = TouchPads(platform.request("touch_pads"))
# Allow the user to reboot the ICE40. Additionally, connect the CPU
# RESET line to a register that can be modified, to allow for
# us to debug programs even during reset.
self.submodules.reboot = SBWarmBoot(self, warmboot_offsets)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.cpu_params.update(
i_externalResetVector=self.reboot.addr.storage,
)
self.submodules.rgb = SBLED(platform.revision, platform.request("rgb_led"))
self.submodules.version = Version(platform.revision, self, pnr_seed, models=[
("0x45", "E", "Fomu EVT"),
("0x44", "D", "Fomu DVT"),
("0x50", "P", "Fomu PVT (production)"),
("0x48", "H", "Fomu Hacker"),
("0x3f", "?", "Unknown model"),
])
# Override default LiteX's yosys/build templates
assert hasattr(platform.toolchain, "yosys_template")
assert hasattr(platform.toolchain, "build_template")
platform.toolchain.yosys_template = [
"{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ice40 -json {build_name}.json -top {build_name}",
]
platform.toolchain.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
"icepack {build_name}.txt {build_name}.bin"
]
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
if use_dsp:
platform.toolchain.yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
if placer is not None:
platform.toolchain.build_template[1] += " --placer {}".format(placer)
def __init__(self, usb_iobuf):
self.bus = wishbone.Interface()
# create a new custom CSR bus
self.submodules.csr = WB2CSR(self.bus)
csr_cpu = self.csr.csr
self.submodules.usb = usb = ClockDomainsRenamer({'sys': 'usb_12'})(
eptri.TriEndpointInterface(usb_iobuf, debug=False))
csrs = self.usb.get_csrs()
# create a CSRBank for the eptri CSRs
self.submodules.csr_bank = ClockDomainsRenamer({'sys': 'usb_12'
})(CSRBank(csrs, 0))
csr_usb12 = self.csr_bank.bus
if hasattr(usb, 'debug_bridge'):
self.debug_bridge = usb.debug_bridge.wishbone
# patch these two CSRs together with an Async FIFO
_layout = [("adr", 32), ("dat_w", 32), ("we", 1)]
self.submodules.fifo = fifo = ClockDomainsRenamer({
'write': 'sys',
'read': 'usb_12'
})(AsyncFIFO(_layout, 64, False))
bus_adr = Signal(32)
self.comb += [
# Data into FIFO
fifo.sink.adr.eq(csr_cpu.adr),
fifo.sink.dat_w.eq(csr_cpu.dat_w),
fifo.sink.we.eq(csr_cpu.we),
fifo.sink.valid.eq(self.csr.en),
# Always clear FIFO on clock cycle
fifo.source.ready.eq(1),
If(
fifo.source.valid,
csr_usb12.dat_w.eq(fifo.source.dat_w),
csr_usb12.adr.eq(fifo.source.adr),
bus_adr.eq(fifo.source.adr),
csr_usb12.we.eq(fifo.source.we),
),
]
self.submodules.fifo_r = fifo_r = ClockDomainsRenamer({
'write': 'usb_12',
'read': 'sys'
})(AsyncFIFO([("adr", 32), ("dat_r", 32)], 64, False))
valid = Signal()
source_adr = Signal(32)
self.sync.usb_12 += [
valid.eq(fifo.source.valid & ~csr_usb12.we),
source_adr.eq(bus_adr)
]
self.comb += [
# Data into FIFO
fifo_r.sink.dat_r.eq(csr_usb12.dat_r),
fifo_r.sink.adr.eq(source_adr),
fifo_r.sink.valid.eq(valid),
fifo_r.source.ready.eq(1),
]
self.sync += [
self.csr.ack.eq(0),
If(
fifo_r.source.valid,
self.csr.ack.eq(self.bus.adr[:14] == fifo_r.source.adr),
csr_cpu.dat_r.eq(fifo_r.source.dat_r),
),
]
# Patch interrupt through
self.irq = Signal()
self.specials += MultiReg(usb.ev.irq, self.irq)
def __init__(self,
pnr_placer="heap", pnr_seed=0, usb_core="dummyusb", usb_bridge=False,
use_dsp=True, **kwargs):
"""Create a basic SoC for the TinyFPGA_BX.
Create a basic SoC for TinyFPGA_BX, including a 48 MHz and 12 MHz clock
domain called `usb_48` and `usb_12`. The `sys` frequency will
run at 16 MHz.
The USB core will optionally have a bridge to the Wishbone bus.
Args:
pnr_placer (str): Which placer to use in nextpnr
pnr_seed (int): Which seed to use in nextpnr
usb_core (str): The name of the USB core to use, if any: dummyusb, epfifo, eptri
usb_bridge (bool): Whether to include a USB-to-Wishbone bridge
Raises:
ValueError: If the `usb_core` is unrecognized
Returns:
Newly-constructed SoC
"""
from litex_boards.platforms.tinyfpga_bx import Platform
platform = Platform()
if "cpu_type" not in kwargs:
kwargs["cpu_type"] = None
kwargs["cpu_variant"] = None
clk_freq = int(16e6)
if "with_uart" not in kwargs:
kwargs["with_uart"] = False
if "with_ctrl" not in kwargs:
kwargs["with_ctrl"] = False
kwargs["integrated_sram_size"] = 0
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
if usb_core is not None:
# Add USB pads. We use DummyUsb, which simply enumerates as a USB
# device. Then all interaction is done via the wishbone bridge.
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
if usb_core == "dummyusb":
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_bridge)
elif usb_core == "epfifo":
self.submodules.usb = epfifo.PerEndpointFifo(usb_iobuf, debug=usb_bridge)
elif usb_core == "eptri":
self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf, debug=usb_bridge)
else:
raise ValueError("unrecognized usb_core: {}".format(usb_core))
if usb_bridge:
self.add_wb_master(self.usb.debug_bridge.wishbone)
# Override default LiteX's yosys/build templates
assert hasattr(platform.toolchain, "yosys_template")
assert hasattr(platform.toolchain, "build_template")
platform.toolchain.yosys_template = [
"{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ice40 -json {build_name}.json -top {build_name}",
]
platform.toolchain.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
"icepack {build_name}.txt {build_name}.bin"
]
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
if use_dsp:
platform.toolchain.yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
if pnr_placer is not None:
platform.toolchain.build_template[1] += " --placer {}".format(pnr_placer)