def pull_write_data(self, counter=None, cond=None):
"""
@return data, mask, valid, last
"""
if self._write_disabled:
raise TypeError('Write disabled.')
if counter is not None and not isinstance(counter, vtypes.Reg):
raise TypeError("counter must be Reg or None.")
if counter is None:
counter = self.write_counters[-1]
ready = make_condition(cond)
val = 1 if ready is None else ready
prev_subst = self.wdata.wready._get_subst()
if not prev_subst:
self.wdata.wready.assign(val)
else:
self.wdata.wready.subst[0].overwrite_right(
vtypes.Ors(prev_subst[0].right, val))
ack = vtypes.Ands(self.wdata.wready, self.wdata.wvalid)
data = self.wdata.wdata
mask = self.wdata.wstrb
valid = ack
last = self.wdata.wlast
self.seq.If(vtypes.Ands(ack, counter > 0))(
counter.dec()
)
return data, mask, valid, last
def pull_write_dataflow(self, counter=None, cond=None):
"""
@return data, mask, last, done
"""
if self._write_disabled:
raise TypeError('Write disabled.')
if counter is not None and not isinstance(counter, vtypes.Reg):
raise TypeError("counter must be Reg or None.")
if counter is None:
counter = self.write_counters[-1]
data_ready = self.m.TmpWire()
mask_ready = self.m.TmpWire()
last_ready = self.m.TmpWire()
data_ready.assign(1)
mask_ready.assign(1)
last_ready.assign(1)
if cond is None:
cond = (data_ready, last_ready)
elif isinstance(cond, (tuple, list)):
cond = tuple(list(cond) + [data_ready, last_ready])
else:
cond = (cond, data_ready, last_ready)
ready = make_condition(*cond)
val = 1 if ready is None else ready
prev_subst = self.wdata.wready._get_subst()
if not prev_subst:
self.wdata.wready.assign(val)
else:
self.wdata.wready.subst[0].overwrite_right(
vtypes.Ors(prev_subst[0].right, val))
ack = vtypes.Ands(self.wdata.wready, self.wdata.wvalid)
data = self.wdata.wdata
mask = self.wdata.wstrb
valid = self.wdata.wvalid
last = self.wdata.wlast
self.seq.If(vtypes.Ands(ack, counter > 0))(
counter.dec()
)
df = self.df if self.df is not None else dataflow
df_data = df.Variable(data, valid, data_ready)
df_mask = df.Variable(mask, valid, mask_ready,
width=self.datawidth // 4)
df_last = df.Variable(last, valid, last_ready, width=1)
done = last
return df_data, df_mask, df_last, done
def push_read_dataflow(self, data, counter=None, cond=None):
"""
@return done
"""
if self._read_disabled:
raise TypeError('Read disabled.')
if counter is not None and not isinstance(counter, vtypes.Reg):
raise TypeError("counter must be Reg or None.")
if counter is None:
counter = self.read_counters[-1]
ack = vtypes.Ands(counter > 0,
vtypes.Ors(self.rdata.rready, vtypes.Not(self.rdata.rvalid)))
last = self.m.TmpReg(initval=0)
if cond is None:
cond = ack
else:
cond = (cond, ack)
raw_data, raw_valid = data.read(cond=cond)
# write condition
self.seq.If(raw_valid)
self.seq.If(vtypes.Ands(ack, counter > 0))(
self.rdata.rdata(raw_data),
self.rdata.rvalid(1),
self.rdata.rlast(0),
counter.dec()
)
self.seq.Then().If(counter == 1)(
self.rdata.rlast(1),
last(1)
)
# de-assert
self.seq.Delay(1)(
self.rdata.rvalid(0),
self.rdata.rlast(0),
last(0)
)
# retry
self.seq.If(vtypes.Ands(self.rdata.rvalid, vtypes.Not(self.rdata.rready)))(
self.rdata.rvalid(self.rdata.rvalid),
self.rdata.rlast(self.rdata.rlast),
last(last)
)
done = last
return done
def write_data(self, data, counter=None, cond=None):
"""
@return ack, last
"""
if self._write_disabled:
raise TypeError('Write disabled.')
if counter is not None and not isinstance(counter, vtypes.Reg):
raise TypeError("counter must be Reg or None.")
if counter is None:
counter = self.write_counters[-1]
if cond is not None:
self.seq.If(cond)
ack = vtypes.Ands(counter > 0,
vtypes.Ors(self.wdata.wready, vtypes.Not(self.wdata.wvalid)))
last = self.m.TmpReg(initval=0)
self.seq.If(vtypes.Ands(ack, counter > 0))(
self.wdata.wdata(data),
self.wdata.wvalid(1),
self.wdata.wlast(0),
self.wdata.wstrb(vtypes.Repeat(
vtypes.Int(1, 1), (self.wdata.datawidth // 8))),
counter.dec()
)
self.seq.Then().If(counter == 1)(
self.wdata.wlast(1),
last(1)
)
# de-assert
self.seq.Delay(1)(
self.wdata.wvalid(0),
self.wdata.wlast(0),
last(0)
)
# retry
self.seq.If(vtypes.Ands(self.wdata.wvalid, vtypes.Not(self.wdata.wready)))(
self.wdata.wvalid(self.wdata.wvalid),
self.wdata.wlast(self.wdata.wlast),
last(last)
)
return ack, last
def write_request(self, addr, length=1, cond=None, counter=None):
"""
@return ack, counter
"""
if self._write_disabled:
raise TypeError('Write disabled.')
if isinstance(length, int) and length > 2 ** self.burst_size_width:
raise ValueError("length must be less than 257.")
if isinstance(length, int) and length < 1:
raise ValueError("length must be more than 0.")
if counter is not None and not isinstance(counter, vtypes.Reg):
raise TypeError("counter must be Reg or None.")
if cond is not None:
self.seq.If(cond)
ack = vtypes.Ors(self.waddr.awready, vtypes.Not(self.waddr.awvalid))
if counter is None:
counter = self.m.TmpReg(self.burst_size_width, initval=0)
self.write_counters.append(counter)
self.seq.If(vtypes.Ands(ack, counter == 0))(
self.waddr.awaddr(addr),
self.waddr.awlen(length - 1),
self.waddr.awvalid(1),
counter(length)
)
self.seq.Then().If(length == 0)(
self.waddr.awvalid(0)
)
# de-assert
self.seq.Delay(1)(
self.waddr.awvalid(0)
)
# retry
self.seq.If(vtypes.Ands(self.waddr.awvalid, vtypes.Not(self.waddr.awready)))(
self.waddr.awvalid(self.waddr.awvalid)
)
return ack, counter
def _setup_sink_ram(self, ram, var, port, set_cond):
if ram._id() in var.sink_ram_id_map:
ram_id = var.sink_ram_id_map[ram._id()]
self.seq.If(set_cond)(
var.sink_ram_sel(ram_id)
)
return
if ram._id() not in self.ram_id_map:
ram_id = self.ram_id_count
self.ram_id_count += 1
self.ram_id_map[ram._id()] = ram_id
else:
ram_id = self.ram_id_map[ram._id()]
var.sink_ram_id_map[ram._id()] = ram_id
self.seq.If(set_cond)(
var.sink_ram_sel(ram_id)
)
ram_cond = (var.sink_ram_sel == ram_id)
wenable = vtypes.Ands(var.sink_ram_wenable, ram_cond)
ram.write_rtl(var.sink_ram_waddr, var.sink_ram_wdata,
port=port, cond=wenable)
def enq(self, wdata, cond=None, delay=0):
""" Enque operation """
if self._enq_disabled:
raise TypeError('Enq disabled.')
if cond is not None:
self.seq.If(cond)
current_delay = self.seq.current_delay
not_full = vtypes.Not(self.wif.full)
ack = vtypes.Ands(not_full, self.wif.enq)
if current_delay + delay == 0:
ready = vtypes.Not(self.wif.almost_full)
else:
ready = self._count + (current_delay + delay + 1) < self._max_size
self.seq.Delay(current_delay + delay).EagerVal().If(not_full)(
self.wif.wdata(wdata))
self.seq.Then().Delay(current_delay + delay)(self.wif.enq(1))
# de-assert
self.seq.Delay(current_delay + delay + 1)(self.wif.enq(0))
return ack, ready
def _setup_source_ram(self, ram, var, port, set_cond):
if ram._id() in var.source_ram_id_map:
ram_id = var.source_ram_id_map[ram._id()]
self.seq.If(set_cond)(
var.source_ram_sel(ram_id)
)
return
if ram._id() not in self.ram_id_map:
ram_id = self.ram_id_count
self.ram_id_count += 1
self.ram_id_map[ram._id()] = ram_id
else:
ram_id = self.ram_id_map[ram._id()]
var.source_ram_id_map[ram._id()] = ram_id
self.seq.If(set_cond)(
var.source_ram_sel(ram_id)
)
ram_cond = (var.source_ram_sel == ram_id)
renable = vtypes.Ands(var.source_ram_renable, ram_cond)
d, v = ram.read_rtl(var.source_ram_raddr, port=port, cond=renable)
add_mux(var.source_ram_rdata, ram_cond, d)
self.seq(
var.source_ram_rvalid(self.seq.Prev(renable, 1))
)
def lock(self, fsm):
name = fsm.name
new_lock_id = self._get_id(name)
if new_lock_id > 2**self.width - 1:
raise ValueError('too many lock IDs')
# try
try_state = fsm.current
state_cond = fsm.state == fsm.current
try_cond = vtypes.Not(self.lock_reg)
fsm_cond = vtypes.Ors(try_cond, self.lock_id == new_lock_id)
self.seq.If(state_cond, try_cond)(self.lock_reg(1),
self.lock_id(new_lock_id))
fsm.If(fsm_cond).goto_next()
# verify
cond = vtypes.Ands(self.lock_reg, self.lock_id == new_lock_id)
fsm.If(vtypes.Not(cond)).goto(try_state) # try again
fsm.If(cond).goto_next() # OK
return 1
def deq(self, cond=None, delay=0):
""" Deque operation """
if self._deq_disabled:
raise TypeError('Deq disabled.')
if cond is not None:
self.seq.If(cond)
not_empty = vtypes.Not(self.rif.empty)
current_delay = self.seq.current_delay
self.seq.Delay(current_delay + delay)(self.rif.deq(1))
rdata = self.rif.rdata
rvalid = self.m.TmpReg(initval=0)
self.seq.Then().Delay(current_delay + delay + 1)(rvalid(
vtypes.Ands(not_empty, self.rif.deq)))
# de-assert
self.seq.Delay(current_delay + delay + 1)(self.rif.deq(0))
self.seq.Delay(current_delay + delay + 2)(rvalid(0))
return rdata, rvalid
def push_read_data(self, data, counter=None, cond=None):
"""
@return ack, last
"""
if self._read_disabled:
raise TypeError('Read disabled.')
if counter is not None and not isinstance(counter, vtypes.Reg):
raise TypeError("counter must be Reg or None.")
if counter is None:
counter = self.read_counters[-1]
if cond is not None:
self.seq.If(cond)
ack = vtypes.Ands(counter > 0,
vtypes.Ors(self.rdata.rready, vtypes.Not(self.rdata.rvalid)))
last = self.m.TmpReg(initval=0)
self.seq.If(vtypes.Ands(ack, counter > 0))(
self.rdata.rdata(data),
self.rdata.rvalid(1),
self.rdata.rlast(0),
counter.dec()
)
self.seq.Then().If(counter == 1)(
self.rdata.rlast(1),
last(1)
)
# de-assert
self.seq.Delay(1)(
self.rdata.rvalid(0),
self.rdata.rlast(0),
last(0)
)
# retry
self.seq.If(vtypes.Ands(self.rdata.rvalid, vtypes.Not(self.rdata.rready)))(
self.rdata.rvalid(self.rdata.rvalid),
self.rdata.rlast(self.rdata.rlast),
last(last)
)
return ack, last
def _make_cond(self, condlist):
ret = None
for cond in condlist:
if ret is None:
ret = cond
else:
ret = vtypes.Ands(ret, cond)
return ret
def _add_statement(self,
statement,
keep=None,
delay=None,
cond=None,
lazy_cond=False,
eager_val=False,
no_delay_cond=False):
cond = make_condition(cond)
if keep is not None:
for i in range(keep):
new_delay = i if delay is None else delay + i
self._add_statement(statement,
keep=None,
delay=new_delay,
cond=cond,
lazy_cond=lazy_cond,
eager_val=eager_val,
no_delay_cond=no_delay_cond)
return self
if delay is not None and delay > 0:
if eager_val:
statement = [
self._add_delayed_subst(s, delay) for s in statement
]
if not no_delay_cond:
if cond is None:
cond = 1
if not lazy_cond:
cond = self._add_delayed_cond(cond, delay)
else: # lazy condition
t = self._add_delayed_cond(1, delay)
if isinstance(cond, int) and cond == 1:
cond = t
else:
cond = vtypes.Ands(t, cond)
statement = [vtypes.If(cond)(*statement)]
self.delayed_body[delay].extend(statement)
self._add_dst_var(statement)
return self
if cond is not None:
statement = [vtypes.If(cond)(*statement)]
self.last_if_statement = statement[0]
self.body.extend(statement)
self._add_dst_var(statement)
return self
def mkFifoDefinition(name, datawidth=32, addrwidth=4):
m = module.Module(name)
clk = m.Input('CLK')
rst = m.Input('RST')
wif = FifoWriteSlaveInterface(m, name, datawidth)
rif = FifoReadSlaveInterface(m, name, datawidth)
mem = m.Reg('mem', datawidth, 2**addrwidth)
head = m.Reg('head', addrwidth, initval=0)
tail = m.Reg('tail', addrwidth, initval=0)
is_empty = m.Wire('is_empty')
is_almost_empty = m.Wire('is_almost_empty')
is_full = m.Wire('is_full')
is_almost_full = m.Wire('is_almost_full')
mask = (2**addrwidth) - 1
is_empty.assign(head == tail)
is_almost_empty.assign(head == ((tail + 1) & mask))
is_full.assign(((head + 1) & mask) == tail)
is_almost_full.assign(((head + 2) & mask) == tail)
rdata = m.Reg('rdata_reg', datawidth, initval=0)
wif.full.assign(is_full)
wif.almost_full.assign(vtypes.Ors(is_almost_full, is_full))
rif.empty.assign(is_empty)
rif.almost_empty.assign(vtypes.Ors(is_almost_empty, is_empty))
seq = Seq(m, '', clk, rst)
seq.If(vtypes.Ands(wif.enq, vtypes.Not(is_full)))(mem[head](wif.wdata),
head.inc())
seq.If(vtypes.Ands(rif.deq, vtypes.Not(is_empty)))(rdata(mem[tail]),
tail.inc())
rif.rdata.assign(rdata)
seq.make_always()
return m
def add_disable_cond(targ, cond, value):
prev_assign = targ._get_assign()
if not prev_assign:
targ.assign(vtypes.Mux(cond, value, 1))
else:
prev_value = prev_assign.statement.right
prev_assign.overwrite_right(
vtypes.Ands(vtypes.Mux(cond, value, 1), prev_value))
targ.module.remove(prev_assign)
targ.module.append(prev_assign)
def pull_read_request(self, cond=None, counter=None):
"""
@return addr, counter, valid
"""
if self._read_disabled:
raise TypeError('Read disabled.')
if counter is not None and not isinstance(counter, vtypes.Reg):
raise TypeError("counter must be Reg or None.")
if counter is None:
counter = self.m.TmpReg(self.burst_size_width, initval=0)
self.read_counters.append(counter)
ready = make_condition(cond)
ack = vtypes.Ands(self.raddr.arready, self.raddr.arvalid)
addr = self.m.TmpReg(self.addrwidth, initval=0)
valid = self.m.TmpReg(initval=0)
val = (vtypes.Not(valid) if ready is None else
vtypes.Ands(ready, vtypes.Not(valid)))
prev_subst = self.raddr.arready._get_subst()
if not prev_subst:
self.raddr.arready.assign(val)
else:
self.raddr.arready.subst[0].overwrite_right(
vtypes.Ors(prev_subst[0].right, val))
self.seq.If(ack)(
addr(self.raddr.araddr),
counter(self.raddr.arlen + 1)
)
self.seq(
valid(ack)
)
return addr, counter, valid
def write_dataflow(self,
port,
addr,
data,
length=1,
stride=1,
cond=None,
when=None):
"""
@return done
'data' and 'when' must be dataflow variables
"""
if self._write_disabled[port]:
raise TypeError('Write disabled.')
counter = self.m.TmpReg(length.bit_length() + 1, initval=0)
last = self.m.TmpReg(initval=0)
ext_cond = make_condition(cond)
data_cond = make_condition(counter > 0, vtypes.Not(last))
if when is None or not isinstance(when, df_numeric):
raw_data, raw_valid = data.read(cond=data_cond)
else:
data_list, raw_valid = read_multi(self.m,
data,
when,
cond=data_cond)
raw_data = data_list[0]
when = data_list[1]
when_cond = make_condition(when, ready=data_cond)
if when_cond is not None:
raw_valid = vtypes.Ands(when_cond, raw_valid)
self.seq.If(ext_cond, counter == 0)(
self.interfaces[port].addr(addr - stride),
counter(length),
)
self.seq.If(raw_valid, counter > 0)(
self.interfaces[port].addr(self.interfaces[port].addr + stride),
self.interfaces[port].wdata(raw_data),
self.interfaces[port].wenable(1), counter.dec())
self.seq.If(raw_valid, counter == 1)(last(1))
# de-assert
self.seq.Delay(1)(self.interfaces[port].wenable(0), last(0))
done = last
return done
def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=4):
self.m = m
self.name = name
self.clk = clk
self.rst = rst
self.datawidth = datawidth
self.addrwidth = addrwidth
self.wif = FifoWriteInterface(self.m, name, datawidth)
self.rif = FifoReadInterface(self.m, name, datawidth)
self.definition = mkFifoDefinition(name, datawidth, addrwidth)
self.inst = self.m.Instance(self.definition, 'inst_' + name,
ports=m.connect_ports(self.definition))
self.seq = Seq(m, name, clk, rst)
# entry counter
self._max_size = (2 ** self.addrwidth - 1 if isinstance(self.addrwidth, int) else
vtypes.Int(2) ** self.addrwidth - 1)
self._count = self.m.Reg(
'count_' + name, self.addrwidth + 1, initval=0)
self.seq.If(
vtypes.Ands(vtypes.Ands(self.wif.enq, vtypes.Not(self.wif.full)),
vtypes.Ands(self.rif.deq, vtypes.Not(self.rif.empty))))(
self._count(self._count)
).Elif(vtypes.Ands(self.wif.enq, vtypes.Not(self.wif.full)))(
self._count.inc()
).Elif(vtypes.Ands(self.rif.deq, vtypes.Not(self.rif.empty)))(
self._count.dec()
)
self._enq_disabled = False
self._deq_disabled = False
self.mutex = None
def _binary_op_div(self, op, r):
lvalue = self.value
lpoint = self.point
lsigned = self.signed
if not isinstance(r, Fixed):
rvalue = r
rsigned = vtypes.get_signed(r)
rpoint = 0
else:
rvalue = r.value
rsigned = r.signed
rpoint = r.point
point = _max_mux(lpoint, rpoint)
signed = lsigned and rsigned
lwidth = lvalue.bit_length()
rwidth = rvalue.bit_length()
ldata, rdata = adjust(lvalue, rvalue, lpoint, rpoint, signed)
try:
lmsb = ldata[lwidth - 1]
except:
lmsb = (ldata >> (lwidth - 1) & 0x1)
try:
rmsb = rdata[lwidth - 1]
except:
rmsb = (rdata >> (rwidth - 1) & 0x1)
abs_ldata = (ldata if not lsigned else
vtypes.Mux(lmsb == 0, ldata, vtypes.Unot(ldata) + 1))
abs_rdata = (rdata if not rsigned else
vtypes.Mux(rmsb == 0, rdata, vtypes.Unot(rdata) + 1))
abs_data = op(abs_ldata, abs_rdata)
data = (abs_data if not signed else
vtypes.Mux(vtypes.Ors(vtypes.Ands(lmsb, rmsb),
vtypes.Ands(vtypes.Not(lmsb), vtypes.Not(rmsb))),
abs_data, vtypes.Unot(abs_data) + 1))
return Fixed(data, point, signed)
def _synthesize_set_sink(self, var, name):
if var.sink_fsm is not None:
return
sink_start = vtypes.Ands(self.start, var.sink_mode == 0,
var.sink_size > 0)
fsm_id = self.fsm_id_count
self.fsm_id_count += 1
prefix = self._prefix(name)
fsm_name = '_%s_sink_fsm_%d' % (prefix, fsm_id)
var.sink_fsm = FSM(self.module, fsm_name, self.clock, self.reset,
as_module=self.fsm_as_module)
self.seq.If(var.sink_fsm.here)(
var.sink_ram_wenable(0)
)
var.sink_fsm.If(sink_start).goto_next()
self.seq.If(var.sink_fsm.here)(
var.sink_ram_waddr(var.sink_offset - var.sink_stride),
var.sink_count(var.sink_size)
)
num_wdelay = self._write_delay()
for _ in range(num_wdelay):
var.sink_fsm.goto_next()
if name in self.sink_when_map:
when = self.sink_when_map[name]
wcond = when.read()
else:
wcond = None
rdata = var.read()
self.seq.If(var.sink_fsm.here)(
var.sink_ram_wenable(0)
)
self.seq.If(var.sink_fsm.here, wcond)(
var.sink_ram_waddr.add(var.sink_stride),
var.sink_ram_wdata(rdata),
var.sink_ram_wenable(1),
var.sink_count.dec()
)
var.sink_fsm.If(wcond, var.sink_count == 1).goto_init()
def If(self, *cond):
self._clear_elif_cond()
cond = make_condition(*cond)
if cond is None:
return self
if 'cond' not in self.next_kwargs:
self.next_kwargs['cond'] = cond
else:
self.next_kwargs['cond'] = vtypes.Ands(self.next_kwargs['cond'],
cond)
self.last_cond = [self.next_kwargs['cond']]
return self
def _synthesize_set_source(self, var, name):
if var.source_fsm is not None:
return
wdata = var.source_ram_rdata
wenable = var.source_ram_rvalid
var.write(wdata, wenable)
source_start = vtypes.Ands(self.start, var.source_mode == 0,
var.source_size > 0)
self.seq.If(source_start)(
var.source_idle(0)
)
fsm_id = self.fsm_id_count
self.fsm_id_count += 1
prefix = self._prefix(name)
fsm_name = '_%s_source_fsm_%d' % (prefix, fsm_id)
var.source_fsm = FSM(self.module, fsm_name, self.clock, self.reset,
as_module=self.fsm_as_module)
var.source_fsm.If(source_start).goto_next()
self.seq.If(var.source_fsm.here)(
var.source_ram_raddr(var.source_offset),
var.source_ram_renable(1),
var.source_count(var.source_size)
)
var.source_fsm.goto_next()
self.seq.If(var.source_fsm.here)(
var.source_ram_raddr.add(var.source_stride),
var.source_ram_renable(1),
var.source_count.dec()
)
self.seq.If(var.source_fsm.here, var.source_count == 1)(
var.source_ram_renable(0),
var.source_idle(1)
)
var.source_fsm.If(var.source_count == 1).goto_init()
def write_dataflow(self, port, addr, data, length=1, cond=None, when=None):
"""
@return done
"""
if self._write_disabled[port]:
raise TypeError('Write disabled.')
counter = self.m.TmpReg(length.bit_length() + 1, initval=0)
last = self.m.TmpReg(initval=0)
ext_cond = make_condition(cond)
data_cond = make_condition(counter > 0, vtypes.Not(last))
all_cond = make_condition(data_cond, ext_cond)
raw_data, raw_valid = data.read(cond=data_cond)
when_cond = make_condition(when, ready=data_cond)
if when_cond is not None:
raw_valid = vtypes.Ands(when_cond, raw_valid)
self.seq.If(make_condition(ext_cond, counter == 0))(
self.interfaces[port].addr(addr - 1),
counter(length),
)
self.seq.If(make_condition(raw_valid, counter > 0))(
self.interfaces[port].addr.inc(),
self.interfaces[port].wdata(raw_data),
self.interfaces[port].wenable(1),
counter.dec()
)
self.seq.If(make_condition(raw_valid, counter == 1))(
last(1)
)
# de-assert
self.seq.Delay(1)(
self.interfaces[port].wenable(0),
last(0)
)
done = last
return done
def deq_rtl(self, cond=None):
""" Deque """
if self._deq_disabled:
raise TypeError('Deq disabled.')
cond = make_condition(cond)
ready = vtypes.Not(self.rif.empty)
if cond is not None:
deq_cond = vtypes.Ands(cond, ready)
else:
deq_cond = ready
util.add_enable_cond(self.rif.deq, deq_cond, 1)
data = self.rif.rdata
valid = self.seq.Prev(deq_cond, 1)
return data, valid, ready
def enq_rtl(self, wdata, cond=None):
""" Enque """
if self._enq_disabled:
raise TypeError('Enq disabled.')
cond = make_condition(cond)
ready = vtypes.Not(self.wif.almost_full)
if cond is not None:
enq_cond = vtypes.Ands(cond, ready)
enable = cond
else:
enq_cond = ready
enable = vtypes.Int(1, 1)
util.add_mux(self.wif.wdata, enable, wdata)
util.add_enable_cond(self.wif.enq, enable, enq_cond)
ack = self.seq.Prev(ready, 1)
return ack, ready
def make_condition(*cond):
_cond = []
for c in cond:
if isinstance(c, (tuple, list)):
_cond.extend(c)
else:
_cond.append(c)
cond = _cond
if not cond:
return None
ret = None
for c in cond:
c = _get_manager_cond(c)
if ret is None:
ret = c
else:
ret = vtypes.Ands(ret, c) if c is not None else ret
return ret
def mkUartRx(baudrate=19200, clockfreq=100 * 1000 * 1000):
m = Module("UartRx")
waitnum = int(clockfreq / baudrate)
clk = m.Input('CLK')
rst = m.Input('RST')
rxd = m.Input('rxd')
dout = m.OutputReg('dout', 8, initval=0)
valid = m.OutputReg('valid', initval=0)
fsm = FSM(m, 'fsm', clk, rst)
mem = m.TmpReg(9, initval=0)
waitcount = m.TmpReg(int(math.log(waitnum, 2)) + 1, initval=0)
fsm(valid(0), waitcount(int(waitnum / 2) - 1),
mem(vtypes.Cat(rxd, mem[1:9])))
fsm.If(rxd == 0).goto_next()
for i in range(10):
if i == 0: # check the start bit again
fsm.If(vtypes.Ands(waitcount == 1, rxd != 0)).goto_init()
fsm.If(waitcount > 0)(waitcount.dec()).Else(
mem(vtypes.Cat(rxd, mem[1:9])), waitcount(waitnum - 1))
fsm.Then().goto_next()
fsm(valid(1), dout(mem[0:9]))
fsm.goto_init()
fsm.make_always()
return m
def read_dataflow_reuse(self,
port,
addr,
length=1,
stride=1,
reuse_size=1,
num_outputs=1,
cond=None,
point=0,
signed=False):
"""
@return data, last, done
"""
if not isinstance(num_outputs, int):
raise TypeError('num_outputs must be int')
data_valid = [self.m.TmpReg(initval=0) for _ in range(num_outputs)]
last_valid = self.m.TmpReg(initval=0)
data_ready = [self.m.TmpWire() for _ in range(num_outputs)]
last_ready = self.m.TmpWire()
for r in data_ready:
r.assign(1)
last_ready.assign(1)
data_ack = vtypes.Ands(*[
vtypes.Ors(r, vtypes.Not(v))
for v, r in zip(data_valid, data_ready)
])
last_ack = vtypes.Ors(last_ready, vtypes.Not(last_valid))
ext_cond = make_condition(cond)
data_cond = make_condition(data_ack, last_ack)
counter = self.m.TmpReg(length.bit_length() + 1, initval=0)
last = self.m.TmpReg(initval=0)
reuse_data = [
self.m.TmpReg(self.datawidth, initval=0)
for _ in range(num_outputs)
]
next_reuse_data = [
self.m.TmpReg(self.datawidth, initval=0)
for _ in range(num_outputs)
]
reuse_count = self.m.TmpReg(reuse_size.bit_length() + 1, initval=0)
fill_reuse_count = self.m.TmpReg(initval=0)
fetch_done = self.m.TmpReg(initval=0)
fsm = TmpFSM(self.m, self.clk, self.rst)
# initial state
fsm.If(ext_cond)(self.interfaces[port].addr(addr - stride),
fetch_done(0), counter(length))
fsm.If(ext_cond, length > 0).goto_next()
# initial prefetch state
for n in next_reuse_data:
fsm(
self.interfaces[port].addr(self.interfaces[port].addr +
stride),
counter(vtypes.Mux(counter > 0, counter - 1, counter)))
fsm.Delay(2)(n(self.interfaces[port].rdata))
fsm.goto_next()
fsm.goto_next()
fsm.goto_next()
# initial update state
for n, r in zip(next_reuse_data, reuse_data):
fsm(r(n))
fsm(fill_reuse_count(1), fetch_done(counter == 0))
fsm.Delay(1)(fill_reuse_count(0))
fsm.goto_next()
# prefetch state
read_start_state = fsm.current
for n in next_reuse_data:
fsm(
self.interfaces[port].addr(self.interfaces[port].addr +
stride),
counter(vtypes.Mux(counter > 0, counter - 1, counter)))
fsm.Delay(2)(n(self.interfaces[port].rdata))
fsm.goto_next()
fsm.goto_next()
fsm.goto_next()
# update state
for n, r in zip(next_reuse_data, reuse_data):
fsm.If(data_cond, reuse_count == 0)(r(n))
fsm.If(data_cond,
reuse_count == 0)(fill_reuse_count(vtypes.Not(fetch_done)),
fetch_done(counter == 0))
fsm.Delay(1)(fill_reuse_count(0))
# next -> prefetch state or initial state
fsm.If(data_cond, reuse_count == 0, counter == 0).goto_init()
fsm.If(data_cond, reuse_count == 0, counter > 0).goto(read_start_state)
# output signal control
self.seq.If(data_cond, last_valid)(last(0), [d(0) for d in data_valid],
last_valid(0))
self.seq.If(fill_reuse_count)(reuse_count(reuse_size))
self.seq.If(data_cond, reuse_count > 0)(reuse_count.dec(),
[d(1) for d in data_valid],
last_valid(1), last(0))
self.seq.If(data_cond, reuse_count == 1, fetch_done)(last(1))
df = self.df if self.df is not None else dataflow
df_last = df.Variable(last, last_valid, last_ready, width=1)
done = last
df_reuse_data = [
df.Variable(d,
v,
r,
width=self.datawidth,
point=point,
signed=signed)
for d, v, r in zip(reuse_data, data_valid, data_ready)
]
return tuple(df_reuse_data + [df_last, done])
def read_dataflow_reuse_pattern(self,
port,
addr,
pattern,
reuse_size=1,
num_outputs=1,
cond=None,
point=0,
signed=False):
"""
@return data, last, done
"""
if not isinstance(pattern, (tuple, list)):
raise TypeError('pattern must be list or tuple.')
if not pattern:
raise ValueError(
'pattern must have one (size, stride) pair at least.')
if not isinstance(pattern[0], (tuple, list)):
pattern = (pattern, )
if not isinstance(num_outputs, int):
raise TypeError('num_outputs must be int')
data_valid = [self.m.TmpReg(initval=0) for _ in range(num_outputs)]
last_valid = self.m.TmpReg(initval=0)
data_ready = [self.m.TmpWire() for _ in range(num_outputs)]
last_ready = self.m.TmpWire()
for r in data_ready:
r.assign(1)
last_ready.assign(1)
data_ack = vtypes.Ands(*[
vtypes.Ors(r, vtypes.Not(v))
for v, r in zip(data_valid, data_ready)
])
last_ack = vtypes.Ors(last_ready, vtypes.Not(last_valid))
ext_cond = make_condition(cond)
data_cond = make_condition(data_ack, last_ack)
next_addr = self.m.TmpWire(self.addrwidth)
offset_addr = self.m.TmpWire(self.addrwidth)
offsets = [
self.m.TmpReg(self.addrwidth, initval=0) for _ in pattern[1:]
]
offset_addr_value = addr
for offset in offsets:
offset_addr_value = offset + offset_addr_value
offset_addr.assign(offset_addr_value)
offsets.insert(0, None)
count_list = [
self.m.TmpReg(out_size.bit_length() + 1, initval=0)
for (out_size, out_stride) in pattern
]
last = self.m.TmpReg(initval=0)
reuse_data = [
self.m.TmpReg(self.datawidth, initval=0)
for _ in range(num_outputs)
]
next_reuse_data = [
self.m.TmpReg(self.datawidth, initval=0)
for _ in range(num_outputs)
]
reuse_count = self.m.TmpReg(reuse_size.bit_length() + 1, initval=0)
fill_reuse_count = self.m.TmpReg(initval=0)
prefetch_done = self.m.TmpReg(initval=0)
fetch_done = self.m.TmpReg(initval=0)
update_addr = None
stride_value = None
carry = None
for offset, count, (out_size,
out_stride) in zip(offsets, count_list, pattern):
if update_addr is None:
update_addr = count == 0
else:
update_addr = vtypes.Mux(carry, count == 0, update_addr)
if stride_value is None:
stride_value = out_stride
else:
stride_value = vtypes.Mux(carry, out_stride, stride_value)
if carry is None:
carry = out_size == 1
else:
carry = vtypes.Ands(carry, out_size == 1)
next_addr.assign(
vtypes.Mux(update_addr, offset_addr,
self.interfaces[port].addr + stride_value))
fsm = TmpFSM(self.m, self.clk, self.rst)
# initial state
fsm.If(ext_cond)(self.interfaces[port].addr(addr - stride_value),
prefetch_done(0), fetch_done(0))
first = True
for offset, count, (out_size,
out_stride) in zip(offsets, count_list, pattern):
fsm.If(ext_cond)(count(out_size) if first else count(out_size -
1), )
if offset is not None:
fsm.If(ext_cond)(offset(0))
first = False
fsm.If(ext_cond).goto_next()
# initial prefetch state
for n in next_reuse_data:
update_count = None
update_offset = None
last_one = None
carry = None
for offset, count, (out_size,
out_stride) in zip(offsets, count_list,
pattern):
fsm.If(update_count)(count.dec())
fsm.If(update_count, count == 0)(count(out_size - 1))
fsm(self.interfaces[port].addr(next_addr))
fsm.Delay(2)(n(self.interfaces[port].rdata))
if offset is not None:
fsm.If(update_offset,
vtypes.Not(carry))(offset(offset + out_stride))
fsm.If(update_offset, count == 0)(offset(0))
if update_count is None:
update_count = count == 0
else:
update_count = vtypes.Ands(update_count, count == 0)
if update_offset is None:
update_offset = vtypes.Mux(out_size == 1, 1, count == 1)
else:
update_offset = vtypes.Ands(update_offset, count == carry)
if last_one is None:
last_one = count == 0
else:
last_one = vtypes.Ands(last_one, count == 0)
if carry is None:
carry = out_size == 1
else:
carry = vtypes.Ands(carry, out_size == 1)
fsm.goto_next()
fsm.If(last_one)(prefetch_done(1))
fsm.goto_next()
fsm.goto_next()
# initial update state
for r, n in zip(reuse_data, next_reuse_data):
fsm(r(n))
fsm(fetch_done(prefetch_done),
fill_reuse_count(vtypes.Not(fetch_done)))
fsm.Delay(1)(fill_reuse_count(0))
fsm.goto_next()
# prefetch state
read_start_state = fsm.current
for n in next_reuse_data:
update_count = None
update_offset = None
last_one = None
carry = None
for offset, count, (out_size,
out_stride) in zip(offsets, count_list,
pattern):
fsm.If(update_count)(count.dec())
fsm.If(update_count, count == 0)(count(out_size - 1))
fsm(self.interfaces[port].addr(next_addr))
fsm.Delay(2)(n(self.interfaces[port].rdata))
if offset is not None:
fsm.If(update_offset,
vtypes.Not(carry))(offset(offset + out_stride))
fsm.If(update_offset, count == 0)(offset(0))
if update_count is None:
update_count = count == 0
else:
update_count = vtypes.Ands(update_count, count == 0)
if update_offset is None:
update_offset = vtypes.Mux(out_size == 1, 1, count == 1)
else:
update_offset = vtypes.Ands(update_offset, count == carry)
if last_one is None:
last_one = count == 0
else:
last_one = vtypes.Ands(last_one, count == 0)
if carry is None:
carry = out_size == 1
else:
carry = vtypes.Ands(carry, out_size == 1)
fsm.goto_next()
fsm.If(last_one)(prefetch_done(1))
fsm.goto_next()
fsm.goto_next()
# update state
for r, n in zip(reuse_data, next_reuse_data):
fsm.If(data_cond, reuse_count == 0)(r(n))
fsm.If(data_cond,
reuse_count == 0)(fetch_done(prefetch_done),
fill_reuse_count(vtypes.Not(fetch_done)))
fsm.Delay(1)(fill_reuse_count(0))
# next -> prefetch state or initial state
fsm.If(data_cond, reuse_count == 0, fetch_done).goto_init()
fsm.If(data_cond, reuse_count == 0,
vtypes.Not(fetch_done)).goto(read_start_state)
# output signal control
self.seq.If(data_cond, last_valid)(last(0), [d(0) for d in data_valid],
last_valid(0))
self.seq.If(fill_reuse_count)(reuse_count(reuse_size))
self.seq.If(data_cond, reuse_count > 0)(reuse_count.dec(),
[d(1) for d in data_valid],
last_valid(1), last(0))
self.seq.If(data_cond, reuse_count == 1, fetch_done)(last(1))
df = self.df if self.df is not None else dataflow
df_last = df.Variable(last, last_valid, last_ready, width=1)
done = last
df_reuse_data = [
df.Variable(d,
v,
r,
width=self.datawidth,
point=point,
signed=signed)
for d, v, r in zip(reuse_data, data_valid, data_ready)
]
return tuple(df_reuse_data + [df_last, done])
def _synthesize_read_fsm(self):
op_id = 1
if op_id in self.read_ops:
""" already synthesized op """
return
if self.read_fsm is not None:
""" new op """
self.read_ops.append(op_id)
return
""" new op and fsm """
fsm = FSM(self.m, '_'.join(['', self.name, 'read_fsm']),
self.clk, self.rst, as_module=self.fsm_as_module)
self.read_fsm = fsm
self.read_ops.append(op_id)
cur_global_addr = self.m.Reg('_'.join(['', self.name, 'read_cur_global_addr']),
self.addrwidth, initval=0)
cur_size = self.m.Reg('_'.join(['', self.name, 'read_cur_size']),
self.addrwidth + 1, initval=0)
rest_size = self.m.Reg('_'.join(['', self.name, 'read_rest_size']),
self.addrwidth + 1, initval=0)
max_burstlen = 2 ** self.burst_size_width
# state 0
if not self.use_global_base_addr:
gaddr = self.read_global_addr
else:
gaddr = self.read_global_addr + self.global_base_addr
fsm.If(self.read_start)(
cur_global_addr(self.mask_addr(gaddr)),
rest_size(self.read_size)
)
fsm.If(self.read_start).goto_next()
# state 1
check_state = fsm.current
self._check_4KB_boundary(fsm, max_burstlen,
cur_global_addr, cur_size, rest_size)
# state 2
ack = self.read_request(cur_global_addr, cur_size, cond=fsm)
fsm.If(ack).goto_next()
accept = vtypes.Ands(self.raddr.arvalid, self.raddr.arready)
fsm.If(accept)(
cur_global_addr.add(optimize(cur_size * (self.datawidth // 8)))
)
fsm.If(accept, rest_size > 0).goto(check_state)
fsm.If(accept, rest_size == 0).goto_next()
for _ in range(self.num_data_delay):
fsm.goto_next()
# state 3
set_idle = self._set_flag(fsm)
self.seq.If(set_idle)(
self.read_idle(1)
)
fsm.goto_init()
