def add_enable_cond(targ, cond, value): prev_assign = targ._get_assign() if not prev_assign: targ.assign(vtypes.Mux(cond, value, 0)) else: prev_value = prev_assign.statement.right prev_assign.overwrite_right(vtypes.Mux(cond, value, prev_value)) targ.module.remove(prev_assign) targ.module.append(prev_assign)
def _saturate_both(raw_val, cond, width=8, max=None, min=None, signed=False): if max is None: max = _max(width, signed) if min is None: min = _min(width, signed) if (isinstance(max, int) and not isinstance(raw_val, int) and vtypes.get_signed(raw_val)): max = vtypes.Int(max, signed=True) return vtypes.Mux(cond, min, vtypes.Mux(raw_val > max, max, raw_val))
def write_adjust(value, point): lpoint = point rvalue = value rsigned = vtypes.get_signed(value) if not isinstance(value, _FixedBase): rpoint = 0 else: rpoint = value.point ldiff = vtypes.Mux(lpoint <= rpoint, 0, lpoint - rpoint) rdiff = vtypes.Mux(lpoint >= rpoint, 0, rpoint - lpoint) v = vtypes.Mux(lpoint > rpoint, shift_left(rvalue, ldiff, rsigned), vtypes.Mux(lpoint < rpoint, shift_right(rvalue, rdiff, rsigned), rvalue)) return v
def dma_read_async(self, fsm, ram, local_addr, global_addr, size, local_stride=1, port=0, ram_method=None): if ram_method is None: ram_method = getattr(ram, 'write_dataflow') ram_method_name = (ram_method.func.__name__ if isinstance(ram_method, functools.partial) else ram_method.__name__) ram_datawidth = (ram.datawidth if ram_method is None else ram.orig_datawidth if 'bcast' in ram_method_name else ram.orig_datawidth if 'block' in ram_method_name else ram.datawidth) if ram_datawidth == self.datawidth: dma_size = size elif ram_datawidth > self.datawidth: pack_size = ram_datawidth // self.datawidth dma_size = (size << int(math.log(pack_size, 2)) if math.log(pack_size, 2) % 1.0 == 0.0 else size * pack_size) else: pack_size = self.datawidth // ram_datawidth shamt = int(math.log(pack_size, 2)) res = vtypes.Mux( vtypes.And(size, 2 ** shamt - 1) > 0, 1, 0) dma_size = (size >> shamt) + res AXIM_for_AXIStreamIn.dma_read_async(self, fsm, global_addr, dma_size) self.streamin.write_ram_async(fsm, ram, local_addr, size, local_stride, port, ram_method)
def fixed_to_real(value, point): if point < 0: return vtypes.SystemTask('itor', fixed_to_int(value, point)) if point == 0: return vtypes.SystemTask('itor', value) if isinstance(value, float): raise TypeError("value is already float.") if isinstance(value, (int, bool)) and isinstance(point, int): mag = 2 ** point return float(value) / mag signed = vtypes.get_signed(value) width = value.bit_length() msb = (value[width - 1] if isinstance(value, vtypes._Variable) else (value >> (width - 1)) & 0x1) v0 = (vtypes.SystemTask('itor', fixed_to_int(value, point)) + vtypes.SystemTask('itor', fixed_to_int_low(value, point)) / vtypes.SystemTask('itor', vtypes.Int(2) ** point)) nv = vtypes.Unot(value) + 1 v1 = ((vtypes.SystemTask('itor', fixed_to_int(nv, point)) + vtypes.SystemTask('itor', fixed_to_int_low(nv, point)) / vtypes.SystemTask('itor', vtypes.Int(2) ** point))) * vtypes.SystemTask('itor', -1) return vtypes.Mux(signed and msb == 0, v0, v1)
def _adjust(self, value): lpoint = self.point if not isinstance(value, Fixed): rvalue = value rsigned = vtypes.get_signed(value) rpoint = 0 else: rvalue = value.value rsigned = value.signed rpoint = value.point ldiff = vtypes.Mux(lpoint <= rpoint, 0, lpoint - rpoint) rdiff = vtypes.Mux(lpoint >= rpoint, 0, rpoint - lpoint) v = vtypes.Mux(lpoint > rpoint, shift_left(rvalue, ldiff, rsigned), vtypes.Mux(lpoint < rpoint, shift_right(rvalue, rdiff, rsigned), rvalue)) return v
def _saturate_overflow(raw_val, width=8, max=None, signed=False): if max is None: max = _max(width, signed) if (isinstance(max, int) and not isinstance(raw_val, int) and vtypes.get_signed(raw_val)): max = vtypes.Int(max, signed=True) return vtypes.Mux(raw_val > max, max, raw_val)
def __init__(self, left, right): lpoint = left.point if isinstance(left, _FixedBase) else 0 rpoint = right.point if isinstance(right, _FixedBase) else 0 lsigned = vtypes.get_signed(left) rsigned = vtypes.get_signed(right) point = _max_mux(lpoint, rpoint) signed = lsigned and rsigned if not self.overwrite_signed else False lwidth = vtypes.get_width(left) rwidth = vtypes.get_width(right) if lpoint <= rpoint: ldata, rdata = adjust(left, right, lpoint, rpoint, signed) shift_size = point else: ldata = left rdata = right shift_size = point - (lpoint - rpoint) try: lmsb = ldata[lwidth - 1] except: lmsb = (ldata >> (lwidth - 1) & vtypes.Int(1, 1, base=2)) try: rmsb = rdata[rwidth - 1] except: rmsb = (rdata >> (rwidth - 1) & vtypes.Int(1, 1, base=2)) abs_ldata = (ldata if not lsigned else vtypes.Mux( vtypes.Ulnot(lmsb), ldata, vtypes.Unot(ldata) + 1)) abs_rdata = (rdata if not rsigned else vtypes.Mux( vtypes.Ulnot(rmsb), rdata, vtypes.Unot(rdata) + 1)) abs_data = vtypes.Divide(abs_ldata, abs_rdata) data = (abs_data if not signed else vtypes.Mux( vtypes.Eq(lmsb, rmsb), abs_data, vtypes.Unot(abs_data) + 1)) if shift_size > 0: data = vtypes.Sll(data, shift_size) _FixedSkipUnaryOperator.__init__(self, data, point, signed)
def shift_right(value, size, signed=True): if isinstance(value, vtypes.Int): value = value.value if isinstance(value, int) and isinstance(size, int): return value >> size if isinstance(value, bool) and isinstance(size, int): return value >> size return vtypes.Mux(signed, vtypes.Sra(value, size), vtypes.Srl(value, size))
def _binary_op_div(self, op, r): lvalue = self.value lpoint = self.point lsigned = self.signed if not isinstance(r, Fixed): rvalue = r rsigned = vtypes.get_signed(r) rpoint = 0 else: rvalue = r.value rsigned = r.signed rpoint = r.point point = _max_mux(lpoint, rpoint) signed = lsigned and rsigned lwidth = lvalue.bit_length() rwidth = rvalue.bit_length() ldata, rdata = adjust(lvalue, rvalue, lpoint, rpoint, signed) try: lmsb = ldata[lwidth - 1] except: lmsb = (ldata >> (lwidth - 1) & 0x1) try: rmsb = rdata[lwidth - 1] except: rmsb = (rdata >> (rwidth - 1) & 0x1) abs_ldata = (ldata if not lsigned else vtypes.Mux(lmsb == 0, ldata, vtypes.Unot(ldata) + 1)) abs_rdata = (rdata if not rsigned else vtypes.Mux(rmsb == 0, rdata, vtypes.Unot(rdata) + 1)) abs_data = op(abs_ldata, abs_rdata) data = (abs_data if not signed else vtypes.Mux(vtypes.Ors(vtypes.Ands(lmsb, rmsb), vtypes.Ands(vtypes.Not(lmsb), vtypes.Not(rmsb))), abs_data, vtypes.Unot(abs_data) + 1)) return Fixed(data, point, signed)
def adjust(left, right, lpoint, rpoint, signed=True): diff_lpoint = vtypes.Mux(rpoint < lpoint, 0, rpoint - lpoint) diff_rpoint = vtypes.Mux(lpoint < rpoint, 0, lpoint - rpoint) ldata = vtypes.Mux(diff_lpoint == 0, left, shift_left(left, diff_lpoint, signed)) rdata = vtypes.Mux(diff_rpoint == 0, right, shift_left(right, diff_rpoint, signed)) _ldata = vtypes.Mux(signed, vtypes.SystemTask('signed', ldata), ldata) _rdata = vtypes.Mux(signed, vtypes.SystemTask('signed', rdata), rdata) return _ldata, _rdata
def read_dataflow(self, port, addr, length=1, stride=1, cond=None, point=0, signed=True): """ @return data, last, done """ data_valid = self.m.TmpReg(initval=0) last_valid = self.m.TmpReg(initval=0) data_ready = self.m.TmpWire() last_ready = self.m.TmpWire() data_ready.assign(1) last_ready.assign(1) data_ack = vtypes.Ors(data_ready, vtypes.Not(data_valid)) last_ack = vtypes.Ors(last_ready, vtypes.Not(last_valid)) ext_cond = make_condition(cond) data_cond = make_condition(data_ack, last_ack) prev_data_cond = self.seq.Prev(data_cond, 1) data = self.m.TmpWireLike(self.interfaces[port].rdata, signed=True) prev_data = self.seq.Prev(data, 1) data.assign(vtypes.Mux(prev_data_cond, self.interfaces[port].rdata, prev_data)) next_valid_on = self.m.TmpReg(initval=0) next_valid_off = self.m.TmpReg(initval=0) next_last = self.m.TmpReg(initval=0) last = self.m.TmpReg(initval=0) counter = self.m.TmpReg(length.bit_length() + 1, initval=0) self.seq.If(data_cond, next_valid_off)( last(0), data_valid(0), last_valid(0), next_valid_off(0) ) self.seq.If(data_cond, next_valid_on)( data_valid(1), last_valid(1), last(next_last), next_last(0), next_valid_on(0), next_valid_off(1) ) self.seq.If(ext_cond, counter == 0, vtypes.Not(next_last), vtypes.Not(last))( self.interfaces[port].addr(addr), counter(length - 1), next_valid_on(1), next_last(length == 1) ) self.seq.If(data_cond, counter > 0)( self.interfaces[port].addr(self.interfaces[port].addr + stride), counter.dec(), next_valid_on(1), next_last(0) ) self.seq.If(data_cond, counter == 1)( next_last(1) ) df_data = self.df.Variable(data, data_valid, data_ready, width=self.datawidth, point=point, signed=signed) df_last = self.df.Variable( last, last_valid, last_ready, width=1, signed=False) done = last return df_data, df_last, done
def _max_mux(a, b): return vtypes.Mux(a > b, a, b)
def read_dataflow(self, port, addr, length=1, cond=None): """ @return data, last, done """ data_valid = self.m.TmpReg(initval=0) last_valid = self.m.TmpReg(initval=0) data_ready = self.m.TmpWire() last_ready = self.m.TmpWire() data_ready.assign(1) last_ready.assign(1) data_ack = vtypes.Ors(data_ready, vtypes.Not(data_valid)) last_ack = vtypes.Ors(last_ready, vtypes.Not(last_valid)) ext_cond = make_condition(cond) data_cond = make_condition(data_ack, last_ack) prev_data_cond = self.seq.Prev(data_cond, 1) all_cond = make_condition(data_cond, ext_cond) data = self.m.TmpWireLike(self.interfaces[port].rdata) prev_data = self.seq.Prev(data, 1) data.assign( vtypes.Mux(prev_data_cond, self.interfaces[port].rdata, prev_data)) counter = self.m.TmpReg(length.bit_length() + 1, initval=0) next_valid_on = self.m.TmpReg(initval=0) next_valid_off = self.m.TmpReg(initval=0) next_last = self.m.TmpReg(initval=0) last = self.m.TmpReg(initval=0) self.seq.If(make_condition(data_cond, next_valid_off))(last(0), data_valid(0), last_valid(0), next_valid_off(0)) self.seq.If(make_condition(data_cond, next_valid_on))(data_valid(1), last_valid(1), last(next_last), next_last(0), next_valid_on(0), next_valid_off(1)) self.seq.If( make_condition(ext_cond, counter == 0, vtypes.Not(next_last), vtypes.Not(last)))( self.interfaces[port].addr(addr), counter(length - 1), next_valid_on(1), ) self.seq.If(make_condition(data_cond, counter > 0))( self.interfaces[port].addr.inc(), counter.dec(), next_valid_on(1), next_last(0)) self.seq.If(make_condition(data_cond, counter == 1))(next_last(1)) df = self.df if self.df is not None else dataflow df_data = df.Variable(data, data_valid, data_ready) df_last = df.Variable(last, last_valid, last_ready, width=1) done = last return df_data, df_last, done
def read_dataflow_pattern(self, port, addr, pattern, cond=None, point=0, signed=False): """ @return data, last, done """ if not isinstance(pattern, (tuple, list)): raise TypeError('pattern must be list or tuple.') if not pattern: raise ValueError( 'pattern must have one (size, stride) pair at least.') if not isinstance(pattern[0], (tuple, list)): pattern = (pattern, ) data_valid = self.m.TmpReg(initval=0) last_valid = self.m.TmpReg(initval=0) data_ready = self.m.TmpWire() last_ready = self.m.TmpWire() data_ready.assign(1) last_ready.assign(1) data_ack = vtypes.Ors(data_ready, vtypes.Not(data_valid)) last_ack = vtypes.Ors(last_ready, vtypes.Not(last_valid)) ext_cond = make_condition(cond) data_cond = make_condition(data_ack, last_ack) prev_data_cond = self.seq.Prev(data_cond, 1) data = self.m.TmpWireLike(self.interfaces[port].rdata) prev_data = self.seq.Prev(data, 1) data.assign( vtypes.Mux(prev_data_cond, self.interfaces[port].rdata, prev_data)) next_valid_on = self.m.TmpReg(initval=0) next_valid_off = self.m.TmpReg(initval=0) next_last = self.m.TmpReg(initval=0) last = self.m.TmpReg(initval=0) running = self.m.TmpReg(initval=0) next_addr = self.m.TmpWire(self.addrwidth) offset_addr = self.m.TmpWire(self.addrwidth) offsets = [ self.m.TmpReg(self.addrwidth, initval=0) for _ in pattern[1:] ] offset_addr_value = addr for offset in offsets: offset_addr_value = offset + offset_addr_value offset_addr.assign(offset_addr_value) offsets.insert(0, None) count_list = [ self.m.TmpReg(out_size.bit_length() + 1, initval=0) for (out_size, out_stride) in pattern ] self.seq.If(data_cond, next_valid_off)(last(0), data_valid(0), last_valid(0), next_valid_off(0)) self.seq.If(data_cond, next_valid_on)(data_valid(1), last_valid(1), last(next_last), next_last(0), next_valid_on(0), next_valid_off(1)) self.seq.If(ext_cond, vtypes.Not(running), vtypes.Not(next_last), vtypes.Not(last))(self.interfaces[port].addr(addr), running(1), next_valid_on(1)) self.seq.If(data_cond, running)(self.interfaces[port].addr(next_addr), next_valid_on(1), next_last(0)) update_count = None update_offset = None update_addr = None last_one = None stride_value = None carry = None for offset, count, (out_size, out_stride) in zip(offsets, count_list, pattern): self.seq.If(ext_cond, vtypes.Not(running), vtypes.Not(next_last), vtypes.Not(last))(count(out_size - 1)) self.seq.If(data_cond, running, update_count)(count.dec()) self.seq.If(data_cond, running, update_count, count == 0)(count(out_size - 1)) if offset is not None: self.seq.If(ext_cond, vtypes.Not(running), vtypes.Not(next_last), vtypes.Not(last))(offset(0)) self.seq.If(data_cond, running, update_offset, vtypes.Not(carry))(offset(offset + out_stride)) self.seq.If(data_cond, running, update_offset, count == 0)(offset(0)) if update_count is None: update_count = count == 0 else: update_count = vtypes.Ands(update_count, count == 0) if update_offset is None: update_offset = vtypes.Mux(out_size == 1, 1, count == 1) else: update_offset = vtypes.Ands(update_offset, count == carry) if update_addr is None: update_addr = count == 0 else: update_addr = vtypes.Mux(carry, count == 0, update_addr) if last_one is None: last_one = count == 0 else: last_one = vtypes.Ands(last_one, count == 0) if stride_value is None: stride_value = out_stride else: stride_value = vtypes.Mux(carry, out_stride, stride_value) if carry is None: carry = out_size == 1 else: carry = vtypes.Ands(carry, out_size == 1) next_addr.assign( vtypes.Mux(update_addr, offset_addr, self.interfaces[port].addr + stride_value)) self.seq.If(data_cond, running, last_one)(running(0), next_last(1)) df = self.df if self.df is not None else dataflow df_data = df.Variable(data, data_valid, data_ready, width=self.datawidth, point=point, signed=signed) df_last = df.Variable(last, last_valid, last_ready, width=1) done = last return df_data, df_last, done
def read_dataflow_reuse(self, port, addr, length=1, stride=1, reuse_size=1, num_outputs=1, cond=None, point=0, signed=False): """ @return data, last, done """ if not isinstance(num_outputs, int): raise TypeError('num_outputs must be int') data_valid = [self.m.TmpReg(initval=0) for _ in range(num_outputs)] last_valid = self.m.TmpReg(initval=0) data_ready = [self.m.TmpWire() for _ in range(num_outputs)] last_ready = self.m.TmpWire() for r in data_ready: r.assign(1) last_ready.assign(1) data_ack = vtypes.Ands(*[ vtypes.Ors(r, vtypes.Not(v)) for v, r in zip(data_valid, data_ready) ]) last_ack = vtypes.Ors(last_ready, vtypes.Not(last_valid)) ext_cond = make_condition(cond) data_cond = make_condition(data_ack, last_ack) counter = self.m.TmpReg(length.bit_length() + 1, initval=0) last = self.m.TmpReg(initval=0) reuse_data = [ self.m.TmpReg(self.datawidth, initval=0) for _ in range(num_outputs) ] next_reuse_data = [ self.m.TmpReg(self.datawidth, initval=0) for _ in range(num_outputs) ] reuse_count = self.m.TmpReg(reuse_size.bit_length() + 1, initval=0) fill_reuse_count = self.m.TmpReg(initval=0) fetch_done = self.m.TmpReg(initval=0) fsm = TmpFSM(self.m, self.clk, self.rst) # initial state fsm.If(ext_cond)(self.interfaces[port].addr(addr - stride), fetch_done(0), counter(length)) fsm.If(ext_cond, length > 0).goto_next() # initial prefetch state for n in next_reuse_data: fsm( self.interfaces[port].addr(self.interfaces[port].addr + stride), counter(vtypes.Mux(counter > 0, counter - 1, counter))) fsm.Delay(2)(n(self.interfaces[port].rdata)) fsm.goto_next() fsm.goto_next() fsm.goto_next() # initial update state for n, r in zip(next_reuse_data, reuse_data): fsm(r(n)) fsm(fill_reuse_count(1), fetch_done(counter == 0)) fsm.Delay(1)(fill_reuse_count(0)) fsm.goto_next() # prefetch state read_start_state = fsm.current for n in next_reuse_data: fsm( self.interfaces[port].addr(self.interfaces[port].addr + stride), counter(vtypes.Mux(counter > 0, counter - 1, counter))) fsm.Delay(2)(n(self.interfaces[port].rdata)) fsm.goto_next() fsm.goto_next() fsm.goto_next() # update state for n, r in zip(next_reuse_data, reuse_data): fsm.If(data_cond, reuse_count == 0)(r(n)) fsm.If(data_cond, reuse_count == 0)(fill_reuse_count(vtypes.Not(fetch_done)), fetch_done(counter == 0)) fsm.Delay(1)(fill_reuse_count(0)) # next -> prefetch state or initial state fsm.If(data_cond, reuse_count == 0, counter == 0).goto_init() fsm.If(data_cond, reuse_count == 0, counter > 0).goto(read_start_state) # output signal control self.seq.If(data_cond, last_valid)(last(0), [d(0) for d in data_valid], last_valid(0)) self.seq.If(fill_reuse_count)(reuse_count(reuse_size)) self.seq.If(data_cond, reuse_count > 0)(reuse_count.dec(), [d(1) for d in data_valid], last_valid(1), last(0)) self.seq.If(data_cond, reuse_count == 1, fetch_done)(last(1)) df = self.df if self.df is not None else dataflow df_last = df.Variable(last, last_valid, last_ready, width=1) done = last df_reuse_data = [ df.Variable(d, v, r, width=self.datawidth, point=point, signed=signed) for d, v, r in zip(reuse_data, data_valid, data_ready) ] return tuple(df_reuse_data + [df_last, done])
def read_dataflow_reuse_pattern(self, port, addr, pattern, reuse_size=1, num_outputs=1, cond=None, point=0, signed=False): """ @return data, last, done """ if not isinstance(pattern, (tuple, list)): raise TypeError('pattern must be list or tuple.') if not pattern: raise ValueError( 'pattern must have one (size, stride) pair at least.') if not isinstance(pattern[0], (tuple, list)): pattern = (pattern, ) if not isinstance(num_outputs, int): raise TypeError('num_outputs must be int') data_valid = [self.m.TmpReg(initval=0) for _ in range(num_outputs)] last_valid = self.m.TmpReg(initval=0) data_ready = [self.m.TmpWire() for _ in range(num_outputs)] last_ready = self.m.TmpWire() for r in data_ready: r.assign(1) last_ready.assign(1) data_ack = vtypes.Ands(*[ vtypes.Ors(r, vtypes.Not(v)) for v, r in zip(data_valid, data_ready) ]) last_ack = vtypes.Ors(last_ready, vtypes.Not(last_valid)) ext_cond = make_condition(cond) data_cond = make_condition(data_ack, last_ack) next_addr = self.m.TmpWire(self.addrwidth) offset_addr = self.m.TmpWire(self.addrwidth) offsets = [ self.m.TmpReg(self.addrwidth, initval=0) for _ in pattern[1:] ] offset_addr_value = addr for offset in offsets: offset_addr_value = offset + offset_addr_value offset_addr.assign(offset_addr_value) offsets.insert(0, None) count_list = [ self.m.TmpReg(out_size.bit_length() + 1, initval=0) for (out_size, out_stride) in pattern ] last = self.m.TmpReg(initval=0) reuse_data = [ self.m.TmpReg(self.datawidth, initval=0) for _ in range(num_outputs) ] next_reuse_data = [ self.m.TmpReg(self.datawidth, initval=0) for _ in range(num_outputs) ] reuse_count = self.m.TmpReg(reuse_size.bit_length() + 1, initval=0) fill_reuse_count = self.m.TmpReg(initval=0) prefetch_done = self.m.TmpReg(initval=0) fetch_done = self.m.TmpReg(initval=0) update_addr = None stride_value = None carry = None for offset, count, (out_size, out_stride) in zip(offsets, count_list, pattern): if update_addr is None: update_addr = count == 0 else: update_addr = vtypes.Mux(carry, count == 0, update_addr) if stride_value is None: stride_value = out_stride else: stride_value = vtypes.Mux(carry, out_stride, stride_value) if carry is None: carry = out_size == 1 else: carry = vtypes.Ands(carry, out_size == 1) next_addr.assign( vtypes.Mux(update_addr, offset_addr, self.interfaces[port].addr + stride_value)) fsm = TmpFSM(self.m, self.clk, self.rst) # initial state fsm.If(ext_cond)(self.interfaces[port].addr(addr - stride_value), prefetch_done(0), fetch_done(0)) first = True for offset, count, (out_size, out_stride) in zip(offsets, count_list, pattern): fsm.If(ext_cond)(count(out_size) if first else count(out_size - 1), ) if offset is not None: fsm.If(ext_cond)(offset(0)) first = False fsm.If(ext_cond).goto_next() # initial prefetch state for n in next_reuse_data: update_count = None update_offset = None last_one = None carry = None for offset, count, (out_size, out_stride) in zip(offsets, count_list, pattern): fsm.If(update_count)(count.dec()) fsm.If(update_count, count == 0)(count(out_size - 1)) fsm(self.interfaces[port].addr(next_addr)) fsm.Delay(2)(n(self.interfaces[port].rdata)) if offset is not None: fsm.If(update_offset, vtypes.Not(carry))(offset(offset + out_stride)) fsm.If(update_offset, count == 0)(offset(0)) if update_count is None: update_count = count == 0 else: update_count = vtypes.Ands(update_count, count == 0) if update_offset is None: update_offset = vtypes.Mux(out_size == 1, 1, count == 1) else: update_offset = vtypes.Ands(update_offset, count == carry) if last_one is None: last_one = count == 0 else: last_one = vtypes.Ands(last_one, count == 0) if carry is None: carry = out_size == 1 else: carry = vtypes.Ands(carry, out_size == 1) fsm.goto_next() fsm.If(last_one)(prefetch_done(1)) fsm.goto_next() fsm.goto_next() # initial update state for r, n in zip(reuse_data, next_reuse_data): fsm(r(n)) fsm(fetch_done(prefetch_done), fill_reuse_count(vtypes.Not(fetch_done))) fsm.Delay(1)(fill_reuse_count(0)) fsm.goto_next() # prefetch state read_start_state = fsm.current for n in next_reuse_data: update_count = None update_offset = None last_one = None carry = None for offset, count, (out_size, out_stride) in zip(offsets, count_list, pattern): fsm.If(update_count)(count.dec()) fsm.If(update_count, count == 0)(count(out_size - 1)) fsm(self.interfaces[port].addr(next_addr)) fsm.Delay(2)(n(self.interfaces[port].rdata)) if offset is not None: fsm.If(update_offset, vtypes.Not(carry))(offset(offset + out_stride)) fsm.If(update_offset, count == 0)(offset(0)) if update_count is None: update_count = count == 0 else: update_count = vtypes.Ands(update_count, count == 0) if update_offset is None: update_offset = vtypes.Mux(out_size == 1, 1, count == 1) else: update_offset = vtypes.Ands(update_offset, count == carry) if last_one is None: last_one = count == 0 else: last_one = vtypes.Ands(last_one, count == 0) if carry is None: carry = out_size == 1 else: carry = vtypes.Ands(carry, out_size == 1) fsm.goto_next() fsm.If(last_one)(prefetch_done(1)) fsm.goto_next() fsm.goto_next() # update state for r, n in zip(reuse_data, next_reuse_data): fsm.If(data_cond, reuse_count == 0)(r(n)) fsm.If(data_cond, reuse_count == 0)(fetch_done(prefetch_done), fill_reuse_count(vtypes.Not(fetch_done))) fsm.Delay(1)(fill_reuse_count(0)) # next -> prefetch state or initial state fsm.If(data_cond, reuse_count == 0, fetch_done).goto_init() fsm.If(data_cond, reuse_count == 0, vtypes.Not(fetch_done)).goto(read_start_state) # output signal control self.seq.If(data_cond, last_valid)(last(0), [d(0) for d in data_valid], last_valid(0)) self.seq.If(fill_reuse_count)(reuse_count(reuse_size)) self.seq.If(data_cond, reuse_count > 0)(reuse_count.dec(), [d(1) for d in data_valid], last_valid(1), last(0)) self.seq.If(data_cond, reuse_count == 1, fetch_done)(last(1)) df = self.df if self.df is not None else dataflow df_last = df.Variable(last, last_valid, last_ready, width=1) done = last df_reuse_data = [ df.Variable(d, v, r, width=self.datawidth, point=point, signed=signed) for d, v, r in zip(reuse_data, data_valid, data_ready) ] return tuple(df_reuse_data + [df_last, done])
def _saturate_underflow(raw_val, cond, width=8, min=None, signed=False): if min is None: min = _min(width, signed) return vtypes.Mux(cond, min, raw_val)
def _min_mux(a, b): return vtypes.Mux(a < b, a, b)
def _synthesize_read_fsm_wide(self, ram, port, ram_method, ram_datawidth): """ axi.datawidth > ram.datawidth """ if self.datawidth % ram_datawidth != 0: raise ValueError( 'axi.datawidth must be multiple number of ram_datawidth') pack_size = self.datawidth // ram_datawidth shamt = int(math.log(pack_size, 2)) res = vtypes.Mux( vtypes.And(self.read_size, 2 ** shamt - 1) > 0, 1, 0) dma_size = (self.read_size >> shamt) + res actual_read_size = dma_size << shamt op_id = self._get_read_op_id(ram, port, ram_method) port = vtypes.to_int(port) if op_id in self.read_ops: """ already synthesized op """ return if pack_size in self.read_wide_fsms: """ new op """ self.read_ops.append(op_id) fsm = self.read_wide_fsms[pack_size] pack_count = self.read_wide_pack_counts[pack_size] data = self.read_wide_data_wires[pack_size] valid = self.read_wide_valid_wires[pack_size] rest_size = self.read_wide_rest_size_wires[pack_size] # state 0 fsm.set_index(0) wdata, wvalid, w = self._get_op_write_dataflow(ram_datawidth) cond = vtypes.Ands(self.read_start, self.read_op_sel == op_id) ram_method(port, self.read_local_addr, w, actual_read_size, stride=self.read_local_stride, cond=cond) fsm.If(cond).goto_next() # state 1 fsm.set_index(1) valid_cond = vtypes.Ands(valid, self.read_op_sel == op_id) stay_cond = self.read_op_sel == op_id fsm.Delay(1)( wvalid(0) ) fsm.If(pack_count == 0, valid_cond)( wdata(data), wvalid(1), pack_count.inc() ) fsm.If(pack_count > 0, stay_cond)( wdata(wdata >> ram_datawidth), wvalid(1), pack_count.inc() ) fsm.If(valid_cond)( rest_size.dec() ) return """ new op and fsm """ fsm = FSM(self.m, '_'.join(['', self.name, 'read_wide', str(pack_size), 'fsm']), self.clk, self.rst, as_module=self.fsm_as_module) self.read_wide_fsms[pack_size] = fsm self.read_ops.append(op_id) rest_size = self.m.Reg('_'.join(['', self.name, 'read_wide', str(pack_size), 'rest_size']), self.addrwidth + 1, initval=0) self.read_wide_rest_size_wires[pack_size] = rest_size # state 0 wdata, wvalid, w = self._get_op_write_dataflow(ram_datawidth) cond = vtypes.Ands(self.read_start, self.read_op_sel == op_id) ram_method(port, self.read_local_addr, w, actual_read_size, stride=self.read_local_stride, cond=cond) fsm.If(self.read_start)( rest_size(dma_size) ) fsm.If(cond).goto_next() # state 1 pack_count = self.m.Reg('_'.join(['', self.name, 'read_wide', str(pack_size), 'pack_count']), int(math.ceil(math.log(pack_size, 2))), initval=0) self.read_wide_pack_counts[pack_size] = pack_count cond = vtypes.Ands(fsm.here, pack_count == 0) data, last, _id, user, dest, valid = self.read_data(cond=cond) self.read_wide_data_wires[pack_size] = data self.read_wide_valid_wires[pack_size] = valid valid_cond = vtypes.Ands(valid, self.read_op_sel == op_id) stay_cond = self.read_op_sel == op_id wlast = self.m.Reg('_'.join(['', self.name, 'read_wide', str(pack_size), 'wlast']), initval=0) fsm.Delay(1)( wvalid(0) ) fsm.If(pack_count == 0, valid_cond)( wdata(data), wvalid(1), wlast(last), pack_count.inc() ) fsm.If(pack_count > 0, stay_cond)( wdata(wdata >> ram_datawidth), wvalid(1), pack_count.inc() ) fsm.If(pack_count == pack_size - 1)( pack_count(0) ) fsm.If(pack_count == 0, valid_cond)( rest_size.dec() ) fsm.If(pack_count == pack_size - 1, rest_size == 0).goto_next() for _ in range(self.num_data_delay): fsm.goto_next() # state 2 set_idle = self._set_flag(fsm) self.seq.If(set_idle)( self.read_idle(1) ) fsm.goto_init()
def dec_part(self): mask = vtypes.Mux(self.point == 0, 0, vtypes.Repeat( vtypes.Int(1, width=1), self.point)) return self & mask
def _synthesize_read_fsm_fifo_wide(self, fifo, fifo_datawidth): """ axi.datawidth > fifo.datawidth """ if self.datawidth % fifo_datawidth != 0: raise ValueError( 'axi.datawidth must be multiple number of fifo_datawidth') pack_size = self.datawidth // fifo_datawidth shamt = int(math.log(pack_size, 2)) res = vtypes.Mux( vtypes.And(self.read_size, 2 ** shamt - 1) > 0, 1, 0) dma_size = (self.read_size >> shamt) + res actual_read_size = dma_size << shamt op_id = self._get_read_op_id_fifo(fifo) if op_id in self.read_ops: """ already synthesized op """ return if pack_size in self.read_wide_fsms: """ new op """ self.read_ops.append(op_id) fsm = self.read_wide_fsms[pack_size] pack_count = self.read_wide_pack_counts[pack_size] data = self.read_wide_data_wires[pack_size] valid = self.read_wide_valid_wires[pack_size] rest_size = self.read_wide_rest_size_wires[pack_size] # state 0 fsm.set_index(0) cond = vtypes.Ands(self.read_start, self.read_op_sel == op_id) fsm.If(cond).goto_next() # state 1 fsm.set_index(1) valid_cond = vtypes.Ands(valid, self.read_op_sel == op_id) stay_cond = self.read_op_sel == op_id fsm.Delay(1)( wvalid(0) ) fsm.If(pack_count == 0, valid_cond)( wdata(data), wvalid(1), pack_count.inc() ) fsm.If(pack_count > 0, stay_cond)( wdata(wdata >> fifo_datawidth), wvalid(1), pack_count.inc() ) fsm.If(valid_cond)( rest_size.dec() ) return """ new op and fsm """ fsm = FSM(self.m, '_'.join(['', self.name, 'read_wide', str(pack_size), 'fsm']), self.clk, self.rst, as_module=self.fsm_as_module) self.read_wide_fsms[pack_size] = fsm self.read_ops.append(op_id) rest_size = self.m.Reg('_'.join(['', self.name, 'read_wide', str(pack_size), 'rest_size']), self.addrwidth + 1, initval=0) self.read_wide_rest_size_wires[pack_size] = rest_size # state 0 cond = vtypes.Ands(self.read_start, self.read_op_sel == op_id) fsm.If(self.read_start)( rest_size(dma_size) ) fsm.If(cond).goto_next() # state 1 pack_count = self.m.Reg('_'.join(['', self.name, 'read_wide', str(pack_size), 'pack_count']), int(math.ceil(math.log(pack_size, 2))), initval=0) self.read_wide_pack_counts[pack_size] = pack_count ready = vtypes.Not(fifo.almost_full) read_cond = vtypes.Ands(fsm.here, ready) cond = vtypes.Ands(fsm.here, pack_count == 0, read_cond) data, last, _id, user, dest, valid = self.read_data(cond=cond) self.read_wide_data_wires[pack_size] = data self.read_wide_valid_wires[pack_size] = valid wdata = self.m.Reg('_'.join(['', self.name, 'read_wide', str(pack_size), 'wdata']), self.datawidth, initval=0) wvalid = self.m.Reg('_'.join(['', self.name, 'read_wide', str(pack_size), 'wvalid'])) valid_cond = vtypes.Ands(valid, self.read_op_sel == op_id) stay_cond = self.read_op_sel == op_id ack, _ = fifo.enq_rtl(wdata, cond=wvalid) wlast = self.m.Reg('_'.join(['', self.name, 'read_wide', str(pack_size), 'wlast']), initval=0) fsm.Delay(1)( wvalid(0) ) fsm.If(pack_count == 0, valid_cond)( wdata(data), wvalid(1), wlast(last), pack_count.inc() ) fsm.If(pack_count > 0, stay_cond)( wdata(wdata >> fifo_datawidth), wvalid(1), pack_count.inc() ) fsm.If(pack_count == pack_size - 1)( pack_count(0) ) fsm.If(pack_count == 0, valid_cond)( rest_size.dec() ) fsm.If(pack_count == pack_size - 1, rest_size == 0).goto_next() # state 2 set_idle = self._set_flag(fsm) self.seq.If(set_idle)( self.read_idle(1) ) fsm.goto_init()