def init_vna():
ref_freq = 40e6
vna = VNA()
source_freq = 6.0e9
lo_freq = source_freq - 2e6
vna.set_tx_mux('iq', sample_input='adc')
vna.lo.freq_to_regs(lo_freq, ref_freq, apwr=0)
vna.source.freq_to_regs(source_freq, ref_freq, apwr=0)
#vna.dither_en(1)
#vna.set_tx_mux('samples', sample_input='adc')
vna.write_sample_time(int(40e6 / 1000 + 100))
#vna.write_sample_time(110000)
vna.write_io(pwdn=0, mixer_enable=0, led=1, adc_oe=0, adc_shdn=0)
vna.write_pll_io(lo_ce=1, source_ce=1, lo_rf=1, source_rf=1)
vna.write_att(0.0)
vna.write_switches(tx_filter=source_freq,
port=2,
rx_sw='rx2',
rx_sw_force=False)
vna.write_pll(vna.source)
vna.write_pll(vna.lo)
vna.write_pll(vna.source)
vna.write_pll(vna.lo)
vna.read_iq()
vna.read_iq()
return vna
if freq > 4.5e9:
vna.write_att(0)
vna.write_switches(tx_filter=freq, port=port, rx_sw='rx1')
source_freq = freq
lo_freq = source_freq - 2e6
lo_f = vna.lo.freq_to_regs(lo_freq, ref_freq, apwr=1)
vna.write_pll(vna.lo)
source_f = vna.source.freq_to_regs(source_freq, ref_freq, apwr=0)
vna.write_pll(vna.source)
if first:
time.sleep(20e-3)
vna.write_pll(vna.lo)
vna.write_pll(vna.source)
first = False
for i in xrange(4):
iq, sw, t = vna.read_iq()
time.sleep(1e-3)
vna.write_tag(tag)
i = 0
while True:
iq, sw, t = vna.read_iq()
if t != tag:
continue
i += 1
iqs[e].setdefault((sw,port), iq)
print freq, sw, 20*np.log10(np.abs(iq))
if i == 4:
break
tag = (tag + 1) % 256
