def axi_set_phase(self, phase=None, # input [PHASE_WIDTH-1:0] phase; wait_phase_en=True, wait_seq=False, quiet=1): """ Set clock phase TODO: Add refresh off/on for changing phase <phase> 8-bit clock phase value (None will use default) <wait_phase_en> compare phase shift to programmed (will not work if the program was restarted) <wait_seq> read and re-send status request to make sure status reflects new data (just for testing, too fast for Python) @param quiet reduce output Returns 1 if success, 0 if timeout (or no wait was performed) """ if phase is None: phase= vrlg.get_default("DLY_PHASE") vrlg.DLY_PHASE=phase & ((1<<vrlg.PHASE_WIDTH)-1) if vrlg.CLKFBOUT_USE_FINE_PS: phase_value = (-vrlg.DLY_PHASE) & ((1<<vrlg.PHASE_WIDTH)-1) if quiet<2: print("SET INVERTED CLOCK PHASE=0x%x (actual value is 0x%x)"%(vrlg.DLY_PHASE, phase_value)) self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE, phase_value) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address else: if quiet<2: print("SET CLOCK PHASE=0x%x"%(vrlg.DLY_PHASE)) self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE,vrlg.DLY_PHASE) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0) # self.target_phase = phase if wait_phase_en: return self.wait_phase(True, wait_seq) return 0
def axi_set_wbuf_delay(self, delay=None): # input [3:0] delay; """ Set write to buffer latency @param delay 4-bit write to buffer signal delay (in mclk clock cycles) if delay is None will restore default values """ if delay is None: delay= vrlg.get_default("DFLT_WBUF_DELAY") vrlg.DFLT_WBUF_DELAY=delay if self.DEBUG_MODE > 1: print("SET WBUF DELAY=0x%x"%delay) self.x393_axi_tasks.write_control_register(vrlg.MCONTR_PHY_16BIT_ADDR+vrlg.MCONTR_PHY_16BIT_WBUF_DELAY, delay & 0xf) # {28'h0, delay});
def axi_set_wbuf_delay(self, delay=None): # input [3:0] delay; """ Set write to buffer latency @param delay 4-bit write to buffer signal delay (in mclk clock cycles) if delay is None will restore default values """ if delay is None: delay = vrlg.get_default("DFLT_WBUF_DELAY") vrlg.DFLT_WBUF_DELAY = delay if self.DEBUG_MODE > 1: print("SET WBUF DELAY=0x%x" % delay) self.x393_axi_tasks.write_control_register( vrlg.MCONTR_PHY_16BIT_ADDR + vrlg.MCONTR_PHY_16BIT_WBUF_DELAY, delay & 0xf) # {28'h0, delay});
def axi_set_phase( self, phase=None, # input [PHASE_WIDTH-1:0] phase; wait_phase_en=True, wait_seq=False, quiet=1): """ Set clock phase TODO: Add refresh off/on for changing phase <phase> 8-bit clock phase value (None will use default) <wait_phase_en> compare phase shift to programmed (will not work if the program was restarted) <wait_seq> read and re-send status request to make sure status reflects new data (just for testing, too fast for Python) @param quiet reduce output Returns 1 if success, 0 if timeout (or no wait was performed) """ if phase is None: phase = vrlg.get_default("DLY_PHASE") vrlg.DLY_PHASE = phase & ((1 << vrlg.PHASE_WIDTH) - 1) if vrlg.CLKFBOUT_USE_FINE_PS: phase_value = (-vrlg.DLY_PHASE) & ((1 << vrlg.PHASE_WIDTH) - 1) if quiet < 2: print("SET INVERTED CLOCK PHASE=0x%x (actual value is 0x%x)" % (vrlg.DLY_PHASE, phase_value)) self.x393_axi_tasks.write_control_register( vrlg.LD_DLY_PHASE, phase_value ) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address else: if quiet < 2: print("SET CLOCK PHASE=0x%x" % (vrlg.DLY_PHASE)) self.x393_axi_tasks.write_control_register( vrlg.LD_DLY_PHASE, vrlg.DLY_PHASE ) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address self.x393_axi_tasks.write_control_register(vrlg.DLY_SET, 0) # self.target_phase = phase if wait_phase_en: return self.wait_phase(True, wait_seq) return 0