def __init__(self):
# Number of programs in the call stack
self.program_cnt = vsc.int_t(10)
# Handles of all programs
self.program_h = []
# Maximum call stack level
self.max_stack_level = vsc.int_t(50)
# Call stack level of each program
self.stack_level = vsc.randsz_list_t(vsc.bit_t(11))
def get_compare_result(self):
val1 = vsc.int_t(rcs.XLEN, self.rs1_value.get_val())
val2 = vsc.int_t(
rcs.XLEN,
self.imm.get_val() if
(self.format
== riscv_instr_format_t.I_FORMAT) else self.rs2_value.val)
if val1.get_val() == val2.get_val():
return compare_result_e["EQUAL"]
elif val1.get_val() < val2.get_val():
return compare_result_e["SMALLER"]
else:
return compare_result_e["LARGER"]
def get_compare_result(self):
val1 = vsc.int_t(rcs.XLEN)
val2 = vsc.int_t(rcs.XLEN)
val1.val = self.rs1_value.val
val2.val = self.imm.val if (
self.format == riscv_instr_format_t.I_FORMAT) \
else self.rs2_value.val
if val1.val == val2.val:
return compare_result_e["EQUAL"]
elif val1.val < val2.val:
return compare_result_e["SMALLER"]
else:
return compare_result_e["LARGER"]
def get_logical_similarity(self):
val1 = vsc.int_t(rcs.XLEN, self.rs1_value.val)
val2 = vsc.int_t(rcs.XLEN)
val2.val = (self.imm.val if self.format == riscv_instr_format_t.I_FORMAT
else self.rs2_value.val)
temp = bin(val1.val ^ val2.val)
bit_difference = len([[ones for ones in temp[2:] if ones=='1']])
if val1.val == val2.val:
return logical_similarity_e["IDENTICAL"]
elif bit_difference == 32:
return logical_similarity_e["OPPOSITE"]
elif bit_difference < 5:
return logical_similarity_e["SIMILAR"]
else:
return logical_similarity_e["DIFFERENT"]
def sample(self):
binary = vsc.int_t(rcs.XLEN)
binary.set_val(get_val(self.trace["binary"], hexa=1))
# TODO: Currently handled using string formatting as part select
# isn't yet supported for global vsc variables
# width is rcs.XLEN+2 because of 0b in the beginning of binary_bin
binary_bin = format(binary.get_val(), '#0{}b'.format(rcs.XLEN + 2))
if binary_bin[-2:] != "11": # TODO: and RV32C in supported_isa
# TODO: sample compressed instruction
pass
if binary_bin[-2:] == "11":
# TODO: sampling
pass
processed_instr_name = self.process_instr_name(self.trace["instr"])
if processed_instr_name in riscv_instr_name_t.__members__:
instr_name = riscv_instr_name_t[processed_instr_name]
instruction = riscv_cov_instr()
instruction.instr = instr_name
# cov_instr is created, time to manually assign attributes
# TODO: This will get fixed later when we get an inst from template
instruction.assign_attributes()
if instruction.group.name in [
"RV32I", "RV32M", "RV32C", "RV64I", "RV64M", "RV64C",
"RV32F", "RV64F", "RV32D", "RV64D", "RV32B", "RV64B"
]:
self.assign_trace_info_to_instr(instruction)
instruction.pre_sample()
self.instr_cg.sample(instruction)
return True
logging.info("Cannot find opcode: {}".format(processed_instr_name))
return False
def get_imm_special_val(self, imm):
if imm.get_val() == 0:
return special_val_e["ZERO_VAL"]
elif self.format == riscv_instr_format_t.U_FORMAT:
# unsigned immediate value
max_val = vsc.int_t(32, (1 << self.imm_len) - 1)
if imm.get_val() == 0:
return special_val_e["MIN_VAL"]
if imm.get_val() == max_val.get_val():
return special_val_e["MAX_VAL"]
else:
# signed immediate value
max_val = vsc.int_t(32, (2**(self.imm_len - 1)) - 1)
min_val = vsc.int_t(32, -2**(self.imm_len - 1))
if min_val.get_val() == imm.get_val():
return special_val_e["MIN_VAL"]
if max_val.get_val() == imm.get_val():
return special_val_e["MAX_VAL"]
return special_val_e["NORMAL_VAL"]
def __init__(self):
self.x = vsc.attr(vsc.int_t(16, i=-2))
def __init__(self):
self.x = vsc.list_t(vsc.int_t(16), init=[-2, -1])
def __init__(self):
self.x = vsc.list_t(
vsc.int_t(16),
init=[random.randint(-2, -1) for _ in range(1)])
def __init__(self):
# Program counter (PC) of the instruction
self.pc = vsc.bit_t(rcs.XLEN)
self.instr = None
# self.gpr = None # destination operand of the instruction
self.binary = vsc.bit_t(32) # Instruction binary
# self.mode = None # Instruction mode
self.trace = "None" # String representation of the instruction
# self.operands = "None" # Instruction operands (srcss/dests)
# self.pad = None # Not used
self.rs1_value = vsc.int_t(rcs.XLEN)
self.rs2_value = vsc.int_t(rcs.XLEN)
self.rs3_value = vsc.int_t(rcs.XLEN)
self.rd_value = vsc.int_t(rcs.XLEN)
self.fs1_value = vsc.int_t(rcs.XLEN)
self.fs2_value = vsc.int_t(rcs.XLEN)
self.fs3_value = vsc.int_t(rcs.XLEN)
self.fd_value = vsc.int_t(rcs.XLEN)
self.mem_addr = vsc.int_t(rcs.XLEN)
self.unaligned_pc = 0
self.unaligned_mem_access = 0
self.compressed = 0
self.branch_hit = 0
self.div_result = None
self.rs1_sign = 0
self.rs2_sign = 0
self.rs3_sign = 0
self.fs1_sign = 0
self.fs2_sign = 0
self.fs3_sign = 0
self.imm_sign = 0
self.rd_sign = 0
self.fd_sign = 0
self.gpr_hazard = hazard_e.NO_HAZARD
self.lsu_hazard = hazard_e.NO_HAZARD
self.rs1_special_value = 0
self.rs2_special_value = 0
self.rs3_special_value = 0
self.rd_special_value = 0
self.imm_special_value = 0
self.compare_result = 0
self.logical_similarity = 0
self.group = None
self.format = None
self.category = None
self.imm_type = None
self.csr = vsc.bit_t(12)
''' TODO: rs2, rs1, rd, group, format, category, imm_type will be
changed to vsc.enum_t once the issue with set/get_val is fixed '''
self.rs2 = 0
self.rs1 = 0
self.rd = 0
self.imm = vsc.int_t(32)
self.has_rs1 = 1
self.has_rs2 = 1
self.has_rd = 1
self.has_imm = 1
self.imm_len = 0
