def __init__(self, name, def_value):
self.name = name
self.value = vsc.rand_uint8_t(def_value)
def __init__(self):
self.x = vsc.rand_uint8_t()
self.y = vsc.rand_uint8_t()
def __init__(self):
self.a = vsc.rand_uint8_t()
def __init__(self):
self.en_one = vsc.uint8_t()
self.en_two = vsc.uint8_t()
self.a = vsc.rand_uint8_t()
def __init__(self):
self.main_program_instr_cnt = vsc.rand_int32_t() # count of main_prog
self.sub_program_instr_cnt = [] # count of sub_prog
self.debug_program_instr_cnt = 0 # count of debug_rom
self.debug_sub_program_instr_cnt = [] # count of debug sub_progrms
self.max_directed_instr_stream_seq = 20
self.data_page_pattern = vsc.rand_enum_t(data_pattern_t)
self.init_delegation()
self.argv = self.parse_args()
self.args_dict = vars(self.argv)
global rcs
rcs = import_module("pygen_src.target." + self.argv.target +
".riscv_core_setting")
self.m_mode_exception_delegation = {}
self.s_mode_exception_delegation = {}
self.m_mode_interrupt_delegation = {}
self.s_mode_interrupt_delegation = {}
# init_privileged_mode default to MACHINE_MODE
self.init_privileged_mode = privileged_mode_t.MACHINE_MODE
self.mstatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.mie = vsc.rand_bit_t(rcs.XLEN - 1)
self.sstatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.sie = vsc.rand_bit_t(rcs.XLEN - 1)
self.ustatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.uie = vsc.rand_bit_t(rcs.XLEN - 1)
self.mstatus_mprv = vsc.rand_bit_t(1)
self.mstatus_mxr = vsc.rand_bit_t(1)
self.mstatus_sum = vsc.rand_bit_t(1)
self.mstatus_tvm = vsc.rand_bit_t(1)
self.mstatus_fs = vsc.rand_bit_t(2)
self.mstatus_vs = vsc.rand_bit_t(2)
self.mtvec_mode = vsc.rand_enum_t(mtvec_mode_t)
self.tvec_alignment = vsc.rand_uint8_t(self.argv.tvec_alignment)
self.fcsr_rm = vsc.rand_enum_t(f_rounding_mode_t)
self.enable_sfence = vsc.rand_bit_t(1)
self.gpr = vsc.rand_list_t(vsc.enum_t(riscv_reg_t), sz=4)
self.scratch_reg = vsc.rand_enum_t(riscv_reg_t)
self.pmp_reg = vsc.rand_enum_t(riscv_reg_t)
self.sp = vsc.rand_enum_t(riscv_reg_t)
self.tp = vsc.rand_enum_t(riscv_reg_t)
self.ra = vsc.rand_enum_t(riscv_reg_t)
self.check_misa_init_val = 0
self.check_xstatus = 1
self.virtual_addr_translation_on = 0
# Commenting out for now
# vector_cfg = riscv_vector_cfg # TODO
# pmp_cfg = riscv_pmp_cfg # TODO
self.mem_region = {
0: {
'name': "region_0",
'size_in_bytes': 4096,
'xwr': 8
},
1: {
'name': "region_1",
'size_in_bytes': 4096 * 16,
'xwr': 8
}
}
self.amo_region = {0: {'name': "amo_0", 'size_in_bytes': 64, 'xwr': 8}}
self.stack_len = 5000
self.s_mem_region = {
0: {
'name': "s_region_0",
'size_in_bytes': 4096,
'xwr': 8
},
1: {
'name': "s_region_1",
'size_in_bytes': 4096,
'xwr': 8
}
}
self.kernel_stack_len = 4000
self.kernel_program_instr_cnt = 400
# list of main implemented CSRs
self.invalid_priv_mode_csrs = []
self.num_of_sub_program = self.argv.num_of_sub_program
self.instr_cnt = self.argv.instr_cnt
self.num_of_tests = self.argv.num_of_tests
self.no_data_page = self.argv.no_data_page
self.no_branch_jump = self.argv.no_branch_jump
self.no_load_store = self.argv.no_load_store
self.no_csr_instr = self.argv.no_csr_instr
self.no_ebreak = self.argv.no_ebreak
self.no_dret = self.argv.no_dret
self.no_fence = self.argv.no_fence
self.no_wfi = self.argv.no_wfi
self.enable_unaligned_load_store = self.argv.enable_unaligned_load_store
self.illegal_instr_ratio = self.argv.illegal_instr_ratio
self.hint_instr_ratio = self.argv.hint_instr_ratio
self.num_of_harts = self.argv.num_of_harts
self.fix_sp = self.argv.fix_sp
self.use_push_data_section = self.argv.use_push_data_section
self.boot_mode_opts = self.argv.boot_mode
# self.isa = self.argv.isa
if self.boot_mode_opts:
logging.info("Got boot mode option - %0s", self.boot_mode_opts)
if self.boot_mode_opts == "m":
self.init_privileged_mode = privileged_mode_t.MACHINE_MODE
elif self.boot_mode_opts == "s":
self.init_privileged_mode = privileged_mode_t.SUPERVISOR_MODE
elif self.boot_mode_opts == "u":
self.init_privileged_mode = privileged_mode_t.USER_MODE
else:
logging.error("Illegal boot mode option - %0s",
self.boot_mode_opts)
self.enable_page_table_exception = self.argv.enable_page_table_exception
self.no_directed_instr = self.argv.no_directed_instr
self.asm_test_suffix = self.argv.asm_test_suffix
self.enable_interrupt = self.argv.enable_interrupt
self.enable_nested_interrupt = self.argv.enable_nested_interrupt
self.enable_timer_irq = self.argv.enable_timer_irq
self.bare_program_mode = self.argv.bare_program_mode
self.enable_illegal_csr_instruction = self.argv.enable_illegal_csr_instruction
self.enable_access_invalid_csr_level = self.argv.enable_access_invalid_csr_level
self.enable_misaligned_instr = self.argv.enable_misaligned_instr
self.enable_dummy_csr_write = self.argv.enable_dummy_csr_write
self.randomize_csr = self.argv.randomize_csr
self.allow_sfence_exception = self.argv.allow_sfence_exception
self.no_delegation = self.argv.no_delegation
self.force_m_delegation = self.argv.force_m_delegation
self.force_s_delegation = self.argv.force_s_delegation
self.support_supervisor_mode = 0
self.disable_compressed_instr = self.argv.disable_compressed_instr
self.require_signature_addr = self.argv.require_signature_addr
if self.require_signature_addr:
self.signature_addr = int(self.argv.signature_addr, 16)
else:
self.signature_addr = 0xdeadbeef
self.gen_debug_section = self.argv.gen_debug_section
self.enable_ebreak_in_debug_rom = self.argv.enable_ebreak_in_debug_rom
self.set_dcsr_ebreak = self.argv.set_dcsr_ebreak
self.num_debug_sub_program = self.argv.num_debug_sub_program
self.enable_debug_single_step = self.argv.enable_debug_single_step
self.single_step_iterations = 0
self.set_mstatus_tw = self.argv.set_mstatus_tw
self.set_mstatus_mprv = self.argv.set_mstatus_mprv
self.min_stack_len_per_program = 10 * (rcs.XLEN / 8)
self.max_stack_len_per_program = 16 * (rcs.XLEN / 8)
self.max_branch_step = 20
self.reserved_regs = vsc.list_t(vsc.enum_t(riscv_reg_t))
self.enable_floating_point = self.argv.enable_floating_point
self.enable_vector_extension = self.argv.enable_vector_extension
self.enable_b_extension = self.argv.enable_b_extension
self.enable_bitmanip_groups = self.argv.enable_bitmanip_groups
self.dist_control_mode = 0
self.category_dist = {}
self.march_isa = self.argv.march_isa
if len(self.march_isa) != 0:
rcs.supported_isa.append(self.march_isa)
if riscv_instr_group_t.RV32C not in rcs.supported_isa:
self.disable_compressed_instr = 1
self.setup_instr_distribution()
self.get_invalid_priv_lvl_csr()
def __init__(self):
self.e = vsc.rand_enum_t(my_e)
self.a = vsc.rand_uint8_t()
def __init__(self):
self.a = vsc.rand_uint8_t()
self.b = vsc.rand_bit_t(1)
def __init__(self):
self.a = vsc.rand_uint8_t()
self.b = vsc.rand_uint8_t()
self.temp = vsc.list_t(vsc.uint8_t())
self.temp = [1, 3, 4, 12, 13, 14]
async def run(self):
tasks = []
cocotb.fork(self.irq_handler())
self.irq_bfm.add_callback(self.irq_cb)
await self.init_dma()
while self.n_complete < self.total_xfers:
t = cocotb.fork(self.run_xfer())
tasks.append(t)
# TODO: Delay a random amount before
# starting the next transfer
# If all channels are occupied, then clean
# up at least enough tasks to allow us to
# proceed
if self.active_xfers == self.n_channels:
desired_active = vsc.rand_uint8_t()
with vsc.randomize_with(desired_active):
desired_active.inside(
vsc.rangelist(vsc.rng(0, self.n_channels - 2)))
print("--> waiting for transfers to complete (" +
str(desired_active) + ")")
while self.active_xfers > int(desired_active):
print("active: " + str(self.active_xfers) + " desired: " +
str(desired_active))
print("--> Wait for first")
await cocotb.triggers.First(*tasks)
print("<-- Wait for first")
# Now, find completed tasks
while len(tasks) > 0:
idx = -1
for i, t in enumerate(tasks):
if t._finished:
idx = i
break
if idx == -1:
print("No more to remove " + str(idx))
break
else:
print("Remove " + str(idx))
tasks.pop(idx)
print("<-- waiting for transfers to complete")
# Wait for any pending transfers to complete
# First, clean out already-completed transfers
while len(tasks) > 0:
idx = -1
for i, t in enumerate(tasks):
if t._finished:
idx = i
break
if idx == -1:
print("No more to remove " + str(idx))
break
else:
print("Remove " + str(idx))
tasks.pop(idx)
if len(tasks) > 0:
await cocotb.triggers.Combine(*tasks)
def __init__(self):
self.l = vsc.rand_list_t(vsc.uint8_t(), sz=5)
self.a = vsc.rand_uint8_t()
def __init__(self):
self.l = vsc.randsz_list_t(vsc.uint8_t())
self.a = vsc.rand_uint8_t()
def __init__(self, name, def_value):
self.name = name
self.enum_test = vsc.rand_enum_t(level_e)
# self.enum_test = vsc.rand_int32_t()
self.value = vsc.rand_uint8_t(def_value)
def __init__(self):
self.name = my_e.A
self.a = vsc.rand_uint8_t(0)
self.b = vsc.rand_list_t(vsc.enum_t(my_e), 4)
def __init__(self):
self.main_program = vsc.rand_uint8_t()
self.total = vsc.rand_uint8_t()
self.sub_program = vsc.rand_list_t(vsc.uint8_t(), sz=10)
def __init__(self):
self.a = vsc.rand_uint8_t()
self.b = vsc.rand_uint8_t()
self.c = vsc.rand_uint8_t()
self.d = vsc.rand_uint8_t()
def test_simple_int(self):
a = vsc.rand_uint8_t()
print("a=" + str(a.get_val()))
self.assertEqual(a.get_val(), 0)
