def test_elaborate_e_project(self): design_unit = Entity('tb_entity', file_name=join("tempdir", "file.vhd")) design_unit.original_file_name = join("tempdir", "other_path", "original_file.vhd") design_unit.generic_names = ["runner_cfg", "tb_path"] config = Configuration("name", design_unit, sim_options={"ghdl.elab_e": True}) simif = GHDLInterface(prefix="prefix", output_path="") simif._vhdl_standard = VHDL.standard("2008") # pylint: disable=protected-access simif._project = Project() # pylint: disable=protected-access simif._project.add_library("lib", "lib_path") # pylint: disable=protected-access self.assertEqual( simif._get_command(config, join('output_path', 'ghdl'), True), # pylint: disable=protected-access [ join('prefix', 'ghdl'), '-e', '--std=08', '--work=lib', '--workdir=lib_path', '-Plib_path', '-o', join('output_path', 'ghdl', 'tb_entity-arch'), 'tb_entity', 'arch' ] )