def test_compile_project_verilog_extra_flags(self, process, check_output): simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.v", "") source_file = project.add_source_file("file.v", "lib", file_type="verilog") source_file.set_compile_option("modelsim.vlog_flags", ["custom", "flags"]) simif.compile_project(project) process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ join(self.prefix_path, "vlog"), "-quiet", "-modelsimini", join(self.output_path, "modelsim.ini"), "custom", "flags", "-work", "lib", "file.v", "-L", "lib", ] check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_extra_flags(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.v", "") source_file = project.add_source_file("file.v", "lib", file_type="verilog") source_file.set_compile_option("modelsim.vlog_flags", ["custom", "flags"]) simif.compile_project(project) process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env()) run_command.assert_called_once_with([join('prefix', 'vlog'), '-sv', '-quiet', '-modelsimini', modelsim_ini, 'custom', 'flags', '-work', 'lib', 'file.v', '-L', 'lib'], env=simif.get_env())
def test_compile_project_vhdl_93(self, process, check_output): simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("93")) simif.compile_project(project) process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ join(self.prefix_path, "vcom"), "-quiet", "-modelsimini", join(self.output_path, "modelsim.ini"), "-93", "-work", "lib", "file.vhd", ] check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"]) simif.compile_project(project, vhdl_standard="2008") process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"]) run_command.assert_called_once_with([join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini, 'custom', 'flags', '-2008', '-work', 'lib', 'file.vhd'])
def test_compile_project_verilog_coverage(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, coverage="best", persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.v", "") project.add_source_file("file.v", "lib", file_type="verilog") simif.compile_project(project, vhdl_standard="2008") process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"]) run_command.assert_called_once_with([join('prefix', 'vlog'), '-sv', '-quiet', '-modelsimini', modelsim_ini, '+cover=best', '-work', 'lib', 'file.v', '-L', 'lib'])
def test_compile_project_vhdl_extra_flags(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"]) simif.compile_project(project) process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"]) run_command.assert_called_once_with([join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini, 'custom', 'flags', '-2008', '-work', 'lib', 'file.vhd'])
def test_compile_project_vhdl_coverage(self, process, check_output): for coverage_off in [False, True]: check_output.reset_mock() write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", output_path=self.output_path, coverage="best", persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") if coverage_off: source_file.set_compile_option("disable_coverage", True) covargs = [] else: covargs = ['+cover=best'] simif.compile_project(project) process.assert_called_once_with( [join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env()) check_output.assert_called_once_with([ join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini ] + covargs + ['-2008', '-work', 'lib', 'file.vhd'], env=simif.get_env())
def test_compile_project_verilog_coverage(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, coverage="best", persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.v", "") project.add_source_file("file.v", "lib", file_type="verilog") simif.compile_project(project) process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"]) run_command.assert_called_once_with([join('prefix', 'vlog'), '-sv', '-quiet', '-modelsimini', modelsim_ini, '+cover=best', '-work', 'lib', 'file.v', '-L', 'lib'])
def test_compile_project_vhdl_coverage(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, coverage="best", persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") simif.compile_project(project, vhdl_standard="2008") process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"]) run_command.assert_called_once_with([join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini, '+cover=best', '-2008', '-work', 'lib', 'file.vhd'], simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_verilog_define(self, process, check_output): simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.v", "") project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"}) simif.compile_project(project) process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) process_args = [ join(self.prefix_path, "vlog"), "-quiet", "-modelsimini", join(self.output_path, "modelsim.ini"), "-work", "lib", "file.v", "-L", "lib", "+define+defname=defval", ] check_output.assert_called_once_with(process_args, env=simif.get_env())
def test_compile_project_verilog_define(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.v", "") project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"}) simif.compile_project(project, vhdl_standard="2008") process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"]) run_command.assert_called_once_with([join('prefix', 'vlog'), '-sv', '-quiet', '-modelsimini', modelsim_ini, '-work', 'lib', 'file.v', '-L', 'lib', '+define+defname=defval'], simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_vhdl_93(self, process, check_output): simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93") simif.compile_project(project) process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini', join(self.output_path, "modelsim.ini"), '-93', '-work', 'lib', 'file.vhd'] check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_define(self, process, check_output): simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.v", "") project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"}) simif.compile_project(project) process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) process_args = [join(self.prefix_path, 'vlog'), '-quiet', '-modelsimini', join(self.output_path, "modelsim.ini"), '-work', 'lib', 'file.v', '-L', 'lib', '+define+defname=defval'] check_output.assert_called_once_with(process_args, env=simif.get_env())
def test_compile_project_verilog_include(self, process, check_output): simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.v", "") project.add_source_file("file.v", "lib", file_type="verilog", include_dirs=["include"]) simif.compile_project(project) process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [join(self.prefix_path, 'vlog'), '-quiet', '-modelsimini', join(self.output_path, "modelsim.ini"), '-work', 'lib', 'file.v', '-L', 'lib', '+incdir+include'] check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, check_output): simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"]) simif.compile_project(project) process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini', join(self.output_path, "modelsim.ini"), 'custom', 'flags', '-2008', '-work', 'lib', 'file.vhd'] check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, check_output): simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"]) simif.compile_project(project) process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini', join(self.output_path, "modelsim.ini"), 'custom', 'flags', '-2008', '-work', 'lib', 'file.vhd'] check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_system_verilog(self, process, check_output): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.sv", "") project.add_source_file("file.sv", "lib", file_type="systemverilog") simif.compile_project(project) process.assert_called_once_with( [join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env()) check_output.assert_called_once_with([ join('prefix', 'vlog'), '-quiet', '-modelsimini', modelsim_ini, '-sv', '-work', 'lib', 'file.sv', '-L', 'lib' ], env=simif.get_env())
def test_compile_project_vhdl_2002(self, process, check_output): simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="2002") simif.compile_project(project) process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ join(self.prefix_path, 'vcom'), '-quiet', '-modelsimini', join(self.output_path, "modelsim.ini"), '-2002', '-work', 'lib', 'file.vhd' ] check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_vhdl_coverage(self, process, check_output): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, coverage="best", persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") simif.compile_project(project) process.assert_called_once_with( [join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env()) check_output.assert_called_once_with([ join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini, '+cover=best', '-2008', '-work', 'lib', 'file.vhd' ], env=simif.get_env())
def test_compile_project_vhdl_93(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93") simif.compile_project(project) process.assert_called_once_with( [join("prefix", "vlib"), "-unix", "lib_path"]) run_command.assert_called_once_with([ join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini, '-93', '-work', 'lib', 'file.vhd' ])
def test_compile_project_verilog_include(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.v", "") project.add_source_file("file.v", "lib", file_type="verilog", include_dirs=["include"]) simif.compile_project(project) process.assert_called_once_with( [join("prefix", "vlib"), "-unix", "lib_path"], env=simif.get_env()) run_command.assert_called_once_with([ join('prefix', 'vlog'), '-quiet', '-modelsimini', modelsim_ini, '-work', 'lib', 'file.v', '-L', 'lib', '+incdir+include' ], env=simif.get_env())
def test_compile_project_verilog_define(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.v", "") project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"}) simif.compile_project(project) process.assert_called_once_with( [join("prefix", "vlib"), "-unix", "lib_path"]) run_command.assert_called_once_with([ join('prefix', 'vlog'), '-sv', '-quiet', '-modelsimini', modelsim_ini, '-work', 'lib', 'file.v', '-L', 'lib', '+define+defname=defval' ])
def test_compile_project_vhdl_93(self, process, run_command): write_file("modelsim.ini", """ [Library] """) modelsim_ini = join(self.output_path, "modelsim.ini") simif = ModelSimInterface(prefix="prefix", modelsim_ini=modelsim_ini, persistent=False) project = Project() project.add_library("lib", "lib_path") write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard="93") simif.compile_project(project) process.assert_called_once_with([join("prefix", "vlib"), "-unix", "lib_path"]) run_command.assert_called_once_with( [join('prefix', 'vcom'), '-quiet', '-modelsimini', modelsim_ini, '-93', '-work', 'lib', 'file.vhd'])