def __init__( self, args, compile_builtins: Optional[bool] = True, vhdl_standard: Optional[str] = None, ): self._args = args self._configure_logging(args.log_level) self._output_path = str(Path(args.output_path).resolve()) if args.no_color: self._printer = NO_COLOR_PRINTER else: self._printer = COLOR_PRINTER def test_filter(name, attribute_names): keep = any(fnmatch(name, pattern) for pattern in args.test_patterns) if args.with_attributes is not None: keep = keep and set(args.with_attributes).issubset(attribute_names) if args.without_attributes is not None: keep = keep and set(args.without_attributes).isdisjoint(attribute_names) return keep self._test_filter = test_filter self._vhdl_standard: VHDLStandard = select_vhdl_standard(vhdl_standard) self._external_preprocessors = [] # type: ignore self._location_preprocessor = None self._check_preprocessor = None self._simulator_class = SIMULATOR_FACTORY.select_simulator() # Use default simulator options if no simulator was present if self._simulator_class is None: simulator_class = SimulatorInterface self._simulator_output_path = str(Path(self._output_path) / "none") else: simulator_class = self._simulator_class self._simulator_output_path = str( Path(self._output_path) / simulator_class.name ) self._create_output_path(args.clean) database = self._create_database() self._project = VCSTProject( database=database, depend_on_package_body=simulator_class.package_users_depend_on_bodies, ) self._test_bench_list = TestBenchList(database=database) self._builtins = Builtins(self, self._vhdl_standard, simulator_class) if compile_builtins: self.add_builtins()
def compile_standard_libraries(vunit_obj, output_path): """ Compile Xilinx standard libraries using Vivado TCL command """ done_token = join(output_path, "all_done.txt") simulator_class = SIMULATOR_FACTORY.select_simulator() if not exists(done_token): print("Compiling standard libraries into %s ..." % abspath(output_path)) simname = simulator_class.name # Vivado calls rivierapro for riviera if simname == "rivierapro": simname = "riviera" run_vivado( join(dirname(__file__), "tcl", "compile_standard_libs.tcl"), tcl_args=[ simname, simulator_class.find_prefix().replace("\\", "/"), output_path, ], ) else: print("Standard libraries already exists in %s, skipping" % abspath(output_path)) for library_name in ["unisim", "unimacro", "unifast", "secureip", "xpm"]: path = join(output_path, library_name) if exists(path): vunit_obj.add_external_library(library_name, path) with open(done_token, "w") as fptr: fptr.write("done")
# -*- coding: utf-8 -*- from os.path import join, dirname, abspath import subprocess from vunit.sim_if.ghdl import GHDLInterface from vunit.sim_if.factory import SIMULATOR_FACTORY from vunit import VUnit, VUnitCLI ################################################################################ ################################################################################ #Check simulator. print("=============================================") simname = SIMULATOR_FACTORY.select_simulator().name code_coverage = (simname == "ghdl" and \ (GHDLInterface.determine_backend("")=="gcc" or \ GHDLInterface.determine_backend("")=="GCC")) print("Simulator = " + simname) print("=============================================") ################################################################################ #VUnit instance. ui = VUnit.from_argv() #Add module sources. test_1_src_lib = ui.add_library("src_lib") test_1_src_lib.add_source_files("exampleRunpy_1.vhd") #Add tb sources. test_1_tb_lib = ui.add_library("tb_lib") test_1_tb_lib.add_source_files("tbVhdlVunitRunpy.vhd")
############################################################################## ############################################################################## #Check GHDL backend. code_coverage=False try: if( GHDLInterface.determine_backend("")=="gcc" or GHDLInterface.determine_backend("")=="GCC"): code_coverage=True else: code_coverage=False except: print("") #Check simulator. print ("=============================================") simulator_class = SIMULATOR_FACTORY.select_simulator() simname = simulator_class.name print (simname) if (simname == "modelsim"): f= open("modelsim.do","w+") f.write("add wave * \nlog -r /*\nvcd file\nvcd add -r /*\n") f.close() print ("=============================================") ############################################################################## ############################################################################## ############################################################################## #Add custom command line argument to standard CLI #Beware of conflicts with existing arguments cli = VUnitCLI()
from os.path import join, dirname from vunit import VUnit, VUnitCLI from vunit.sim_if.factory import SIMULATOR_FACTORY from run_support import run_with_compile_errors root = dirname(__file__) vhdl_standard = ("2019" if SIMULATOR_FACTORY.select_simulator().name == "rivierapro" else "2008") args = VUnitCLI().parse_args() # keep_going is a planned VUnit feature which adds support for dealing with testbenches # that don't compile if "keep_going" in args: args.keep_going = True ui = VUnit.from_args(args, vhdl_standard=vhdl_standard) vhdl_2008 = ui.add_library("vhdl_2008") vhdl_2019 = ui.add_library("vhdl_2019") vhdl_2008.add_source_files(join(root, "vhdl_2008", "*.vhd")) vhdl_2019.add_source_files(join(root, "vhdl_2019", "*.vhd")) if "keep_going" in args: ui.main() else: # Workaround while keep_going isn't supported run_with_compile_errors(ui, args, vhdl_standard)
from functools import reduce from vunit.test.report import TestReport, PASSED, FAILED from vunit import ostools ROOT = Path(__file__).resolve().parent def vunit_from_args(args, vhdl_standard): ui = VUnit.from_args(args, vhdl_standard=vhdl_standard) for std in ["2008", "2019"]: lib = f"vhdl_{std}" ui.add_library(lib).add_source_files(ROOT / lib / "*.vhd") return ui vhdl_standard = "2019" if SIMULATOR_FACTORY.select_simulator( ).name == "rivierapro" else "2008" args = VUnitCLI().parse_args() ui = vunit_from_args(args, vhdl_standard) # Run all tests in isolation to handle failure to compile args.minimal = True original_test_patterns = args.test_patterns test_report = TestReport() n_tests = 0 total_start_time = ostools.get_time() for tb in (ui.library("vhdl_2008").get_test_benches() + ui.library("vhdl_2019").get_test_benches()): tests = tb.get_tests() for test_name in [test.name for test in tests] if tests else ["all"]: full_test_name = f"{tb.library.name!s}.{tb.name!s}.{test_name!s}" if not reduce(