def test_adding_ports_to_entity(self):
entity = VHDLEntity("name")
entity.add_port("foo", "inout", "foo_t")
self.assertEqual(len(entity.ports), 1)
self.assertEqual(entity.ports[0].identifier, "foo")
self.assertEqual(entity.ports[0].mode, "inout")
self.assertEqual(entity.ports[0].subtype_indication.type_mark, "foo_t")
def test_adding_generics_to_entity(self):
entity = VHDLEntity("name")
entity.add_generic("max_value", "boolean", "20")
self.assertEqual(len(entity.generics), 1)
self.assertEqual(entity.generics[0].identifier, "max_value")
self.assertEqual(entity.generics[0].subtype_indication.type_mark, "boolean")
self.assertEqual(entity.generics[0].init_value, "20")
def test_adding_ports_to_entity(self):
entity = VHDLEntity("name")
entity.add_port("foo", "inout", "foo_t")
self.assertEqual(len(entity.ports), 1)
self.assertEqual(entity.ports[0].identifier, "foo")
self.assertEqual(entity.ports[0].mode, "inout")
self.assertEqual(entity.ports[0].subtype_indication.type_mark, "foo_t")
def test_adding_generics_to_entity(self):
entity = VHDLEntity("name")
entity.add_generic("max_value", "boolean", "20")
self.assertEqual(len(entity.generics), 1)
self.assertEqual(entity.generics[0].identifier, "max_value")
self.assertEqual(entity.generics[0].subtype_indication.type_mark, "boolean")
self.assertEqual(entity.generics[0].init_value, "20")
def _create_entity():
"""
Helper function to create a VHDLEntity
"""
data_width = VHDLInterfaceElement("data_width",
VHDLSubtypeIndication.parse("natural := 16"))
clk = VHDLInterfaceElement("clk",
VHDLSubtypeIndication.parse("std_logic"),
"in")
data = VHDLInterfaceElement("data",
VHDLSubtypeIndication.parse("std_logic_vector(data_width-1 downto 0)"),
"out")
entity = VHDLEntity(identifier="name",
generics=[data_width],
ports=[clk, data])
return entity
