def __init__(self, depend_on_package_body=False, database=None): """ depend_on_package_body - Package users depend also on package body """ self._database = database self._vhdl_parser = VHDLParser(database=self._database) self._verilog_parser = VerilogParser(database=self._database) self._libraries = OrderedDict() # Mapping between library lower case name and real library name self._lower_library_names_dict = {} self._source_files_in_order = [] self._manual_dependencies = [] self._depend_on_package_body = depend_on_package_body self._builtin_libraries = set(["ieee", "std"])
def __init__(self, depend_on_components=False, depend_on_package_body=False, vhdl_parser=VHDLParser(), verilog_parser=VerilogParser()): """ depend_on_package_body - Package users depend also on package body """ self._vhdl_parser = vhdl_parser self._verilog_parser = verilog_parser self._libraries = OrderedDict() self._source_files_in_order = [] self._manual_dependencies = [] self._depend_on_components = depend_on_components self._depend_on_package_body = depend_on_package_body
def __init__(self, depend_on_package_body=False, vhdl_parser=None, verilog_parser=None): """ depend_on_package_body - Package users depend also on package body """ self._vhdl_parser = VHDLParser() if vhdl_parser is None else vhdl_parser self._verilog_parser = VerilogParser() if verilog_parser is None else verilog_parser self._libraries = OrderedDict() # Mapping between library lower case name and real library name self._lower_libray_names_dict = {} self._source_files_in_order = [] self._manual_dependencies = [] self._depend_on_package_body = depend_on_package_body