コード例 #1
0
ファイル: project.py プロジェクト: vmfox/vunit
    def _find_dependencies(self, design_file):
        """
        Return a list of dependencies of this source_file based on the
        use clause and entity instantiations
        """
        # Find dependencies introduced by the use clause
        result = []
        for ref in design_file.references:
            ref = ref.copy()

            if ref.library == "work":
                # Work means same library as current file
                ref.library = self.library.name

            result.append(ref)

        for configuration in design_file.configurations:
            result.append(VHDLReference('entity', self.library.name, configuration.entity, 'all'))

        return result
コード例 #2
0
ファイル: test_vhdl_parser.py プロジェクト: zberkes/vunit
    def test_parsing_references(self):
        design_file = VHDLDesignFile.parse("""
library name1;
 use name1.foo.all;

library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use name1.bla.all;

library lib1,lib2, lib3;
use lib1.foo, lib2.bar,lib3.xyz;

context name1.is_identifier;

entity work1.foo1
entity work1.foo1(a1)
for all : bar use entity work2.foo2
for all : bar use entity work2.foo2 (a2)
for foo : bar use configuration work.cfg

entity foo is -- False
configuration bar of ent -- False

package new_pkg is new lib.pkg;
""")
        self.assertEqual(len(design_file.references), 14)
        self.assertEqual(sorted(design_file.references, key=repr), sorted([
            VHDLReference('configuration', 'work', 'cfg', None),
            VHDLReference('context', 'name1', 'is_identifier', None),
            VHDLReference('entity', 'work1', 'foo1', 'a1'),
            VHDLReference('entity', 'work1', 'foo1', None),
            VHDLReference('entity', 'work2', 'foo2', 'a2'),
            VHDLReference('entity', 'work2', 'foo2', None),
            VHDLReference('package', 'ieee', 'numeric_std', 'all'),
            VHDLReference('package', 'ieee', 'std_logic_1164', 'all'),
            VHDLReference('package', 'lib1', 'foo', None),
            VHDLReference('package', 'lib2', 'bar', None),
            VHDLReference('package', 'lib3', 'xyz', None),
            VHDLReference('package', 'name1', 'bla', 'all'),
            VHDLReference('package', 'name1', 'foo', 'all'),
            VHDLReference('package', 'lib', 'pkg', None),
        ], key=repr))
コード例 #3
0
ファイル: test_vhdl_parser.py プロジェクト: nfrancque/vunit
    def test_parsing_references(self):
        design_file = VHDLDesignFile.parse(
            """
library name1;
 use name1.foo.all;

library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use name1.bla.all;

library lib1,lib2, lib3;
use lib1.foo, lib2.bar,lib3.xyz;

context name1.is_identifier;

entity work1.foo1
entity work1.foo1(a1)
for all : bar use entity work2.foo2
for all : bar use entity work2.foo2 (a2)
for foo : bar use configuration work.cfg

entity foo is -- False
configuration bar of ent -- False

package new_pkg is new lib.pkg;
"""
        )
        self.assertEqual(len(design_file.references), 14)
        self.assertEqual(
            sorted(design_file.references, key=repr),
            sorted(
                [
                    VHDLReference("configuration", "work", "cfg", None),
                    VHDLReference("context", "name1", "is_identifier", None),
                    VHDLReference("entity", "work1", "foo1", "a1"),
                    VHDLReference("entity", "work1", "foo1", None),
                    VHDLReference("entity", "work2", "foo2", "a2"),
                    VHDLReference("entity", "work2", "foo2", None),
                    VHDLReference("package", "ieee", "numeric_std", "all"),
                    VHDLReference("package", "ieee", "std_logic_1164", "all"),
                    VHDLReference("package", "lib1", "foo", None),
                    VHDLReference("package", "lib2", "bar", None),
                    VHDLReference("package", "lib3", "xyz", None),
                    VHDLReference("package", "name1", "bla", "all"),
                    VHDLReference("package", "name1", "foo", "all"),
                    VHDLReference("package", "lib", "pkg", None),
                ],
                key=repr,
            ),
        )