def __init__(self): # config self.cli = VUnitCLI() self.args = self.cli.parse_args() self.args.num_threads = 4 self.ui = VUnit.from_args(self.args) self.lib = self.ui.add_library("lib")
def get_args(root): """ Create and extract command line arguments """ cli = VUnitCLI() cli.parser.add_argument( '-s', '--vendor-verification', action='store_true', help='Use vendor ieee library for internal package references.') cli.parser.add_argument( '-a', '--vhdl-assert-stop-level', default="all", choices=["all", "warning", "error", "failure"], help=('VHDL assert stop level. "all" will use all levels.')) args = cli.parse_args() if args.xunit_xml is None: args.xunit_xml = str(root / "result.xml") xunit_xml_path = Path(args.xunit_xml) if xunit_xml_path.exists(): xunit_xml_path.unlink() return args
def __init__(self): # config self.cli = VUnitCLI() self.args = self.cli.parse_args() self.args.gtkwave_fmt = 'vcd' self.args.num_threads = 4 #self.args.log_level = 'info' self.ui = VUnit.from_args(self.args) self.lib = self.ui.add_library("lib")
def setup_vunit(argv=None): ''' Sets up vunit logging and returns the VUnit object. ''' args = VUnitCLI().parse_args(argv=argv) log_level = args.log_level vu = VUnit.from_args(args) vu.log_level = getattr(logging, log_level.upper()) return vu
class vhdlScript(object): def __init__(self, log): # config self.cli = VUnitCLI() self.args = self.cli.parse_args() self.args.num_threads = 4 self.args.xunit_xml = log self.ui = VUnit.from_args(args=self.args) self.lib = self.ui.add_library("lib") def add_src_lib(self, path): for filename in os.listdir(path): if(filename.split(".")[-1] == "vhd"): if filename[0] != '.': self.lib.add_source_files(path+filename) def useLib(self, lib): self.lib = lib def addSrc(self, pwd): print("-----------------") print(pwd) print("-----------------") self.add_src_lib(pwd) def addTstConfigFile(self, tst): f = util.openConfigFile(tst) if f is not False: for l in f: ls = l.strip() if ls and ('#' not in l): if ls[-4:] == '.vhd': self.addSrcFile(tst + "testes/tb_" + ls) return(True) else: return(False) def addSrcFile(self, f): self.lib.add_source_files(f) def run(self): try: self.ui._main_run(None) return(0) except: return(-1)
class vhdlScript(object): def __init__(self): # config self.cli = VUnitCLI() self.args = self.cli.parse_args() self.args.gtkwave_fmt = 'vcd' self.args.num_threads = 4 self.ui = VUnit.from_args(self.args) self.lib = self.ui.add_library("lib") def add_src_lib(self, path): for filename in os.listdir(path): if (filename.split(".")[-1] == "vhd"): self.lib.add_source_files(path + filename) def useLib(self, lib): self.lib = lib def addSrc(self, pwd): self.add_src_lib(pwd) def run(self): self.ui.main()
class vhdlScript(object): def __init__(self): # config self.cli = VUnitCLI() self.args = self.cli.parse_args() self.args.num_threads = 4 self.ui = VUnit.from_args(self.args) self.lib = self.ui.add_library("lib") def add_src_lib(self, path): for filename in os.listdir(path): if (filename.split(".")[-1] == "vhd"): if filename[0] != '.': self.lib.add_source_files(path + filename) def useLib(self, lib): self.lib = lib def addSrc(self, pwd): print("-----------------") print(pwd) print("-----------------") self.add_src_lib(pwd) def addTstConfigFile(self, tst): f = openConfigFile(tst) if f is not False: for l in f: if l.strip(): if '#' not in l: self.addSrcFile(tst + "tst/tb_" + l[:-1]) def addSrcFile(self, f): self.lib.add_source_files(f) def run(self): self.ui.main()
def main(): "Main entry point for DVB FPGA test runner" _generateGnuRadioData() _createLdpcTables() cli = VUnitCLI() cli.parser.add_argument( "--individual-config-runs", "-i", action="store_true", help="Create individual test runs for each configuration. By default, " "all combinations of frame lengths, code rates and modulations are " "tested in the same simulation", ) args = cli.parse_args() vunit = VUnit.from_args(args=args) vunit.add_osvvm() vunit.add_com() vunit.enable_location_preprocessing() if vunit.get_simulator_name() == "ghdl": vunit.add_preprocessor(GhdlPragmaHandler()) library = vunit.add_library("lib") library.add_source_files(p.join(ROOT, "rtl", "*.vhd")) library.add_source_files(p.join(ROOT, "rtl", "ldpc", "*.vhd")) library.add_source_files(p.join(ROOT, "rtl", "bch_generated", "*.vhd")) library.add_source_files(p.join(ROOT, "testbench", "*.vhd")) vunit.add_library("str_format").add_source_files( p.join(ROOT, "third_party", "hdl_string_format", "src", "*.vhd")) vunit.add_library("fpga_cores").add_source_files( p.join(ROOT, "third_party", "fpga_cores", "src", "*.vhd")) vunit.add_library("fpga_cores_sim").add_source_files( p.join(ROOT, "third_party", "fpga_cores", "sim", "*.vhd")) if args.individual_config_runs: # BCH encoding doesn't depend on the constellation type, choose any for config in _getConfigs( constellations=(ConstellationType.MOD_8PSK, )): vunit.library("lib").entity("axi_bch_encoder_tb").add_config( name=config.name, generics=dict( test_cfg=config.getTestConfigString(), NUMBER_OF_TEST_FRAMES=8, ), ) vunit.library("lib").entity("dvbs2_tx_tb").add_config( name=config.name, generics=dict( test_cfg=config.getTestConfigString(), NUMBER_OF_TEST_FRAMES=2, ), ) # Only generate configs for 8 PSK since LDPC does not depend on this # parameter for config in _getConfigs( constellations=(ConstellationType.MOD_8PSK, ), ): vunit.library("lib").entity("axi_ldpc_encoder_tb").add_config( name=config.name, generics=dict( test_cfg=config.getTestConfigString(), NUMBER_OF_TEST_FRAMES=3, ), ) else: addAllConfigsTest( entity=vunit.library("lib").entity("axi_bch_encoder_tb"), configs=TEST_CONFIGS, ) addAllConfigsTest( entity=vunit.library("lib").entity("axi_ldpc_encoder_tb"), configs=_getConfigs( constellations=(ConstellationType.MOD_8PSK, ), ), ) addAllConfigsTest( entity=vunit.library("lib").entity("dvbs2_tx_tb"), configs=tuple(TEST_CONFIGS), ) addAllConfigsTest( entity=vunit.library("lib").entity("axi_baseband_scrambler_tb"), configs=TEST_CONFIGS, ) # Generate bit interleaver tests for data_width in (1, 8): all_configs = [] for config in _getConfigs(): all_configs += [config.getTestConfigString()] if args.individual_config_runs: vunit.library("lib").entity( "axi_bit_interleaver_tb").add_config( name=f"data_width={data_width},{config.name}", generics=dict( DATA_WIDTH=data_width, test_cfg=config.getTestConfigString(), NUMBER_OF_TEST_FRAMES=8, ), ) if not args.individual_config_runs: vunit.library("lib").entity("axi_bit_interleaver_tb").add_config( name=f"data_width={data_width},all_parameters", generics=dict( DATA_WIDTH=data_width, test_cfg="|".join(all_configs), NUMBER_OF_TEST_FRAMES=2, ), ) vunit.set_compile_option("modelsim.vcom_flags", ["-explicit"]) # Not all options are supported by all GHDL backends vunit.set_sim_option("ghdl.elab_flags", ["-frelaxed-rules"]) vunit.set_compile_option("ghdl.a_flags", ["-frelaxed-rules", "-O2", "-g"]) # Make components not bound (error 3473) an error vsim_flags = ["-error", "3473"] if args.gui: vsim_flags += ['-voptargs="+acc=n"'] vunit.set_sim_option("modelsim.vsim_flags", vsim_flags) vunit.set_sim_option("disable_ieee_warnings", True) vunit.set_sim_option("modelsim.init_file.gui", p.join(ROOT, "wave.do")) vunit.main()
# Make vunit python module importable. Can be removed if vunit is on you pythonpath # environment variable import sys path_to_vunit = join(dirname(__file__), '..', '..', '..') sys.path.append(path_to_vunit) # ------- from vunit import VUnit, VUnitCLI root = dirname(__file__) # These lines add the option to specify the Bitvis Utility Library root directory # from the command line (python run.py -b <path to my BVUL root>). They # can be replaced by a single line, ui = VUnit.from_argv(), if you assign the root # directory to the bvul_root variable directly cli = VUnitCLI() cli.parser.add_argument('-b', '--bvul-root', required=True, help='Bitvis Utility Library root directory') args = cli.parse_args() ui = VUnit.from_args(args) # ------ # Create VHDL libraries and add the related BVUL files to these bvul_root = args.bvul_root bvul_lib = ui.add_library('bitvis_util') bvul_lib.add_source_files(join(bvul_root, 'bitvis_util', 'src2008', '*.vhd')) bitvis_vip_spi_lib = ui.add_library('bitvis_vip_sbi') bitvis_vip_spi_lib.add_source_files(join(bvul_root, 'bitvis_vip_sbi', 'src', '*.vhd'))
depth_b = int(depth_a * width_a / width_b) for reg in oreg: # due to memory model limitation if not (width_a == 32 and width_b == 32): test.add_config( name= "deptha=%d,depthb=%d,widtha=%d,widthb=%d,reg=%s" % (depth_a, depth_b, width_a, width_b, reg), generics=dict(g_width_a=width_a, g_width_b=width_b, g_depth_a=depth_a, g_depth_b=depth_b, g_register=reg)) if __name__ == "__main__": cli = VUnitCLI() cli.parser.add_argument('--cover', type=int, default=0, help='Enable ghdl coverage') args = cli.parse_args() VU = VUnit.from_args(args=args) VU.add_osvvm() create_test_suite(VU, args) if args.cover < 1: VU.main() else: VU.main(post_run=post_run)
from os.path import join, dirname from vunit import VUnit, VUnitCLI from vunit.simulator_factory import SIMULATOR_FACTORY from run_support import run_with_compile_errors root = dirname(__file__) vhdl_standard = ("2019" if SIMULATOR_FACTORY.select_simulator().name == "rivierapro" else "2008") args = VUnitCLI().parse_args() # keep_going is a planned VUnit feature which adds support for dealing with testbenches # that don't compile if "keep_going" in args: args.keep_going = True ui = VUnit.from_args(args, vhdl_standard=vhdl_standard) vhdl_2008 = ui.add_library("vhdl_2008") vhdl_2019 = ui.add_library("vhdl_2019") vhdl_2008.add_source_files(join(root, "vhdl_2008", "*.vhd")) vhdl_2019.add_source_files(join(root, "vhdl_2019", "*.vhd")) if "keep_going" in args: ui.main() else: # Workaround while keep_going isn't supported run_with_compile_errors(ui, args, vhdl_standard)
def setup_vunit(argv=None): args = VUnitCLI().parse_args(argv=argv) log_level = args.log_level vu = VUnit.from_args(args) vu.log_level = getattr(logging, log_level.upper()) return vu
from vunit import ostools ROOT = Path(__file__).resolve().parent def vunit_from_args(args, vhdl_standard): ui = VUnit.from_args(args, vhdl_standard=vhdl_standard) for std in ["2008", "2019"]: lib = f"vhdl_{std}" ui.add_library(lib).add_source_files(ROOT / lib / "*.vhd") return ui vhdl_standard = "2019" if SIMULATOR_FACTORY.select_simulator( ).name == "rivierapro" else "2008" args = VUnitCLI().parse_args() ui = vunit_from_args(args, vhdl_standard) # Run all tests in isolation to handle failure to compile args.minimal = True original_test_patterns = args.test_patterns test_report = TestReport() n_tests = 0 total_start_time = ostools.get_time() for tb in (ui.library("vhdl_2008").get_test_benches() + ui.library("vhdl_2019").get_test_benches()): tests = tb.get_tests() for test_name in [test.name for test in tests] if tests else ["all"]: full_test_name = f"{tb.library.name!s}.{tb.name!s}.{test_name!s}" if not reduce( lambda found_match, pattern: found_match | fnmatch(