def get_file_list(section_case, src_design):
# say_it(section_case, "Section Case:")
_file_list = section_case.get("file list")
_file_list = re.split(",", _file_list)
_file_list = [item.strip() for item in _file_list]
file_list = list()
tb_file = ""
uut_name = ""
p_tb = re.compile("(\w+)_tb$", re.I)
for item in _file_list:
fname = get_fname(item)
fext = get_fext_lower(item)
item = win2unix(item, 0)
m_tb = p_tb.search(fname)
if m_tb:
tb_file = item
continue
if fext in (".v", ".vhd", ".sv"):
file_list.append(item)
else:
say_it("Warning. %s found in _qas.info" % item)
if tb_file:
new_tb_file = get_relative_path(tb_file, src_design)
if not os.path.isfile(new_tb_file):
say_it("-Error. Not found testbench file: %s" % tb_file)
else:
base_module_name = ""
for item in ("module", "project"):
base_module_name = section_case.get(item)
if base_module_name:
break
if not base_module_name:
say_it("Error. Not found base module name")
return tb_file, file_list, uut_name
p_uut_name_verilog = re.compile("%s\s+(\w+)" % base_module_name)
# add_16_SIGNED post(
p_uut_name_vhdl = re.compile("(\S+)\s*:\s*%s" % base_module_name)
# uut: mac_ecp4_m5678_09x09_ir_or_dc_mclk_up PORT MAP(
fext = get_fext_lower(new_tb_file)
if fext == ".v":
matched_uut_name = simple_parser(new_tb_file, [
p_uut_name_verilog,
])
else:
matched_uut_name = simple_parser(new_tb_file, [
p_uut_name_vhdl,
])
if not matched_uut_name:
say_it("-Warning. can not find uut name in %s" % tb_file)
else:
uut_name = matched_uut_name[1].group(1)
return tb_file, file_list, uut_name
def run_pre_post_process(base_path, pp_scripts):
"""
add function for getting the real scripts if it has command arguments
"""
pp_scripts_list = re.split("\s+", pp_scripts)
real_pp = xTools.get_abs_path(pp_scripts_list[0], base_path)
if xTools.not_exists(real_pp, "pre/post process scripts"):
return 1
start_from_dir, pp = os.path.split(real_pp)
_recov = xTools.ChangeDir(start_from_dir)
fext = xTools.get_fext_lower(real_pp)
if fext == ".py":
cmd_line = "%s %s " % (sys.executable, pp)
elif fext == ".pl":
cmd_line = "perl %s " % pp
else:
xTools.say_it("Unknown pre/post process scripts: %s" % pp)
return 1
if len(pp_scripts_list) > 1:
cmd_line += " ".join(pp_scripts_list[1:])
xTools.say_it("Launching %s" % cmd_line)
#sts, text = xTools.get_status_output(cmd_line)
#xTools.say_it(text)
sts = os.system(cmd_line)
_recov.comeback()
return sts
def get_lse_pre_str(self, src):
fext = xTools.get_fext_lower(src)
if fext in (".v", ".vo"):
pre_str = "-ver"
elif fext in (".vhd", ".vhdl", ".vho"):
pre_str = "-vhd"
else:
#xTools.say_it("Warning. Unknown source file: %s" % src)
pre_str = ""
return pre_str
def vcom_vlog_file_lines(hdl_files, vcom_cmd, vlog_cmd, work_name):
cmpl_lines = list()
for item in hdl_files:
fext = xTools.get_fext_lower(item)
if fext == ".v":
cmd_exe = vlog_cmd
else:
cmd_exe = vcom_cmd
cmpl_lines.append("%s -work %s %s" % (cmd_exe, work_name, item))
return cmpl_lines
def add_vlog_vcom_lines(self, src_files, add_tb=0):
self.use_vhd = 0
if add_tb and not self.normal_tb: # use them directly.
v_v_lines = src_files[:]
else:
v_v_lines = list()
for item in src_files:
fext = xTools.get_fext_lower(item)
item = xTools.win2unix(item, 0)
if fext in (".v", ".vo", ".sv"):
v_v_lines.append("vlog %s" % item)
elif fext in (".vho", ".vhd", ".vhdl"):
v_v_lines.append("vcom %s" % item)
if not self.use_vhd:
self.use_vhd = 1
elif fext == ".lpf":
continue
else:
xTools.say_it("-Warning. Unknown file: %s" % item)
continue
return v_v_lines
def get_real_hdl_file(real_hdl_file, run_scuba):
if not run_scuba:
return 0, real_hdl_file
is_model_file = xReport.file_simple_parser(
real_hdl_file, [re.compile("\S+scuba\.exe(.+)")], 80)
if not is_model_file:
return 0, real_hdl_file
# find scuba command!
fext = xTools.get_fext_lower(real_hdl_file)
new_fext = fext
if fext == ".vhd":
if run_scuba in ("verilog", "reverse"):
new_fext = ".v"
elif fext == ".v":
if run_scuba in ("vhdl", "reverse"):
new_fext = ".vhd"
new_file = os.path.splitext(real_hdl_file)[0] + new_fext
if new_fext == fext:
return 0, new_file
else:
return 1, new_file
def parse_file_list(self):
file_list = self.case_info.get("File List")
if not file_list:
xTools.say_it("Error. Not found File List in %s" % self.qas_file)
return 1
# ---------------------------------------------
file_list = re.split(",", file_list)
p_tb = re.compile("_tb\W")
tb_file, src_files = "", list()
for item in file_list:
item = item.strip()
if not item: continue
item = xTools.get_relative_path(item, self.qas_root)
if p_tb.search(item):
tb_file = item
else:
fext = xTools.get_fext_lower(item)
if fext in (".v", ".vhd", ".sv"):
src_files.append(item)
else:
xTools.say_it("Warning. Will skip the file %s" % item)
return tb_file, src_files
def get_lib_file(hdl_type, family_path):
lib_files = list()
p_hdl_type = re.compile("(.+)\Wvhdl\W(\w+)$")
if hdl_type == "verilog":
for foo in os.listdir(family_path):
fext = xTools.get_fext_lower(foo)
if fext == ".v":
lib_files.append(os.path.join(family_path, foo))
elif fext == ".vhd":
xTools.say_it("Warning. found vhd file in %s" % family_path)
else: # vhdl
mti_path = os.path.join(family_path, "mti")
src_path = os.path.join(family_path, "src")
list_v, list_vhd = list(), list()
m = p_hdl_type.search(family_path)
if m:
outside_verilog_path = os.path.join(m.group(1), "verilog",
m.group(2))
if xTools.not_exists(outside_verilog_path,
"Verilog simulation path"):
pass
else:
for v_file in ("GSR.v", "PUR.v"):
real_v = os.path.join(outside_verilog_path, v_file)
if os.path.isfile(real_v):
list_v.append(real_v)
pseudo_v = "pseudo_pullup.v"
if os.path.isfile(pseudo_v):
pass
else:
xTools.write_file(pseudo_v, v_file_lines)
list_v.append(os.path.abspath(pseudo_v))
for foo in os.listdir(src_path):
fext = xTools.get_fext_lower(foo)
abs_foo = os.path.join(src_path, foo)
if fext == ".v":
list_v.append(abs_foo)
elif fext == ".vhd":
list_vhd.append(abs_foo)
else:
xTools.say_it("Warning. found unknown file %s" % abs_foo)
recov = xTools.ChangeDir(mti_path)
if sys.platform[:3] == "win":
bat_file = "orc_cmpl.bat"
else:
bat_file = "orc_cmpl.csh"
already_have_v = 0
for line in open(bat_file):
line = line.strip()
if line.startswith("rem"): continue
if not line: continue
line_list = re.split("\s+", line)
if line_list[0] in ("vcom", "vlog"):
hdl_file = os.path.abspath(line_list[-1])
if os.path.isfile(hdl_file):
lib_files.append(hdl_file)
else:
if re.search("\*\.v", line_list[-1]):
lib_files += list_v
already_have_v = 1
else:
xTools.say_it("Warning. un-support line: %s" % line)
if not already_have_v:
lib_files = list_v + lib_files
recov.comeback()
return lib_files
def _run_simulation(self, sim_path, source_files, user_options):
if xTools.wrap_md(sim_path, "Simulation Path"):
return 1
_recov = xTools.ChangeDir(sim_path)
if self.copy_tb_files(""):
_recov.comeback()
return 1
use_source_do_file = 0
if not user_options: # rtl simulation
if self.others_path:
self.copy_other_files()
src_lines = xTools.get_content_in_start_end(
self.do_template, self.p_src_start, self.p_src_end)
for src in src_lines:
if re.search("(vlog|vcom)", src):
use_source_do_file = 1
do_lines = list()
need_remove_ovi = 0
if use_source_do_file: # modify do file and use it!
start_source = 0
start_tb = 0
for line in open(self.do_template):
line = line.rstrip()
m_src_start = self.p_src_start.search(line)
m_src_end = self.p_src_end.search(line)
m_tb_start = self.p_tb_start.search(line)
m_tb_end = self.p_tb_end.search(line)
if not start_source:
start_source = m_src_start
if m_src_end:
start_source = 0
if not start_tb:
start_tb = m_tb_start
if m_tb_end:
start_tb = 0
if not (start_source or start_tb):
do_lines.append(line)
elif start_source or start_tb:
new_line = get_new_real_path(self.do_template, line)
if start_source:
line_list = re.split("\s+", line.strip())
if line_list[0] in ("vlog", "vcom"):
hdl_file = line_list[-1]
real_hdl_file = xTools.get_relative_path(
hdl_file, os.getcwd())
if not os.path.isfile(real_hdl_file):
real_hdl_file = xTools.get_relative_path(
hdl_file, os.path.join("../../sim"))
if not os.path.isfile(real_hdl_file):
pass
else:
modified, real_hdl_file = get_real_hdl_file(
real_hdl_file, self.run_scuba)
cur_fext = xTools.get_fext_lower(real_hdl_file)
if modified:
if cur_fext == ".vhd":
line_list = ["vcom", ""]
else:
line_list = ["vlog", ""]
line_list[-1] = real_hdl_file
if not need_remove_ovi:
if xTools.get_fext_lower(
real_hdl_file) in (".vho", ".vhd",
".vhdl"):
need_remove_ovi = 1
new_line = " ".join(line_list)
do_lines.append(new_line)
else:
start_source = start_tb = 0
for line in open(self.do_template):
line = line.rstrip()
if re.search("%", line):
line = line % self.do_args
do_lines.append(line)
continue
if start_source:
if self.p_src_end.search(line):
if not user_options: # RTL simulation
source_files = [
xTools.get_relative_path(
item, self.dst_design)
for item in source_files
]
v_v_line = self.add_vlog_vcom_lines(source_files)
if not v_v_line:
xTools.say_it(
"Error. Not any source files for running %s" %
sim_path)
xTools.say_it("")
_recov.comeback()
return 1
need_remove_ovi = self.use_vhd
do_lines += v_v_line[:]
start_source = 0
do_lines.append(line)
continue
else:
start_source = self.p_src_start.search(line)
if start_source:
do_lines.append(line)
continue
if start_tb:
if self.p_tb_end.search(line):
_kk = self.use_vhd
v_v_line = self.add_vlog_vcom_lines(
self.final_tb_files, add_tb=1)
self.use_vhd = _kk
do_lines += v_v_line[:]
start_tb = 0
do_lines.append(line)
continue
else:
start_tb = self.p_tb_start.search(line)
if start_tb:
do_lines.append(line)
continue
do_lines.append(line)
do_file = "do_%s.do" % sim_path
new_do_lines = list()
lib_name = xTools.get_fname(self.dev_lib)
if need_remove_ovi:
lib_name = re.sub("ovi_", "", lib_name)
p1 = re.compile("vmap\s+(\S+)\s+(\$dev_lib)")
p2 = ""
tmp_lib_name = ""
for _ in do_lines:
if p1:
m1 = p1.search(_)
if m1:
p1 = ""
p2 = re.compile("vsim.+\s+-L\s+%s" % m1.group(1))
tmp_lib_name = m1.group(1)
_ = "vmap %s %s" % (lib_name, m1.group(2))
elif p2:
m2 = p2.search(_)
if m2:
p2 = ""
_ = re.sub("-L\s+%s" % tmp_lib_name, "-L %s" % lib_name, _)
new_do_lines.append(_)
xTools.write_file(do_file, new_do_lines)
utils.update_simulation_do_file(self.sim_vendor_name, do_file,
self.lst_precision)
args = "%s %s %s cmd %s %s" % (do_file, self.dev_lib, self.pri_lib,
self.diamond, self.src_lib)
if self.run_modelsim or self.run_questasim:
sim_cmd = '%s/vsim -l sim_log.txt -c -do "do %s"' % (
self.sim_vendor_bin, args)
else:
sim_cmd = "%s/vsimsa -l sim_log.txt -do %s" % (self.sim_vendor_bin,
args)
sim_cmd = xTools.win2unix(sim_cmd, 0)
if need_remove_ovi:
sim_cmd = re.sub("ovi_", "", sim_cmd)
# /*
# * If license not found, will launch again in 10 times.
# */
log_file = "run_%s.log" % sim_path
time_file = "run_%s.time" % sim_path
sts = 0
for i in range(10):
if xTools.remove_dir_without_error(log_file):
_recov.comeback()
return 1
sts = xTools.run_command(sim_cmd, log_file, time_file)
if sts:
if xTools.simple_parser(
log_file,
[re.compile("Unable to checkout a license")]):
xTools.say_it(
"Warning. No licence for running simulation. waiting ..."
)
time.sleep(i * 10)
else:
break
else:
break
dump_vcd_file()
_recov.comeback()
return sts
def prepare_kwargs(self):
self.conf = self.flow_options.get("conf")
same_ldf_dir = self.flow_options.get("same_ldf_dir")
use_ice_prj = self.flow_options.get("use_ice_prj")
self.kwargs = dict()
if use_ice_prj:
_project = self.flow_options.get("Project")
implmnt_path = _project.get("Implementations")
if not implmnt_path:
xTools.say_it(
"-Error. Not found Implementations in project file")
return 1
self.kwargs["ProjectName"] = _project.get("ProjectName",
"DEF_PRJ_NAME")
self.kwargs["implmnt_path"] = implmnt_path
_src_files = _project.get("ProjectVFiles")
_sdc_file = _project.get("ProjectCFiles")
if _sdc_file:
_sdc_file = xTools.get_relative_path(_sdc_file, same_ldf_dir)
sdc_file = self.flow_options.get("sdc_file")
ldc_file = self.flow_options.get("ldc_file")
if sdc_file:
sdc_file = xTools.get_relative_path(sdc_file, same_ldf_dir)
if ldc_file:
ldc_file = xTools.get_relative_path(ldc_file, same_ldf_dir)
_src_files = re.split(",", _src_files)
_src_files = [re.sub("=\w+", "", item) for item in _src_files]
_src_files = [[xTools.get_relative_path(item, same_ldf_dir)]
for item in _src_files]
#####################
_implmnt = self.flow_options.get(implmnt_path)
if not _implmnt:
xTools.say_it("Error. Not found section: %s" % implmnt_path)
return 1
self.kwargs["DeviceFamily"] = _implmnt.get("DeviceFamily")
self.kwargs["Device"] = _implmnt.get("Device")
self.kwargs["DevicePackage"] = _implmnt.get("DevicePackage")
else:
_devkit = self.flow_options.get("devkit")
_top_name = self.flow_options.get("top_module")
_src_files = self.flow_options.get("src_files")
_sdc_file = ""
for item in _src_files:
fext = xTools.get_fext_lower(item)
if fext == ".sdc":
_sdc_file = item
break
sdc_file = self.flow_options.get("sdc_file")
ldc_file = self.flow_options.get("ldc_file")
if sdc_file:
sdc_file = xTools.get_relative_path(sdc_file, same_ldf_dir)
if ldc_file:
ldc_file = xTools.get_relative_path(ldc_file, same_ldf_dir)
_src_files = [[xTools.get_relative_path(item, same_ldf_dir)]
for item in _src_files]
implmnt_path = _top_name + "_Implmnt"
_implmnt = dict()
self.kwargs["ProjectName"] = _top_name
self.kwargs["implmnt_path"] = implmnt_path
self.kwargs["source_files"] = _src_files
_dev_list = re.split("\s*,\s*", _devkit)
self.kwargs["DeviceFamily"], self.kwargs["Device"], self.kwargs[
"DevicePackage"] = _dev_list
# --------------
self.synthesis = self.flow_options.get("synthesis")
if not self.synthesis:
self.synthesis = "synplify"
if self.synthesis == "synplify":
_source_files = super_run.get_synp_source_files(_src_files)
if sdc_file:
kk = sdc_file
elif _sdc_file:
kk = _sdc_file
else:
kk = ""
if kk:
sdc_file = "add_file -constraint %s" % kk
else:
sdc_file = ""
else:
_source_files = super_run.get_lse_source_files(_src_files)
if ldc_file:
sdc_file = "-sdc %s" % ldc_file
else:
sdc_file = ""
self.kwargs["source_files"] = _source_files
self.kwargs["sdc_file"] = sdc_file
# --------------
_goal = self.flow_options.get("goal")
_frequency = self.flow_options.get("frequency")
if not _frequency:
if self.synthesis == "lse":
_frequency = 200
else:
_frequency = "Auto"
_mixed_drivers = xTools.get_true(self.flow_options, "mixed_drivers")
if _mixed_drivers:
_mixed_drivers = "-resolve_mixed_drivers 1" # For LSE
else:
_mixed_drivers = ""
self.kwargs["mixed_drivers"] = _mixed_drivers
if not _goal:
_goal = "Timing"
self.kwargs["goal"] = _goal
self.kwargs["frequency"] = _frequency
_DesignCell = _implmnt.get("DesignCell")
if not _DesignCell:
_DesignCell = self.kwargs["ProjectName"]
self.kwargs["DesignCell"] = _DesignCell
self.kwargs["cwd"] = xTools.win2unix(os.getcwd())
self.kwargs["ice_opt_path"] = self.ice_opt_path
ice_map_file = os.path.join(self.conf, "ice_synthesis", "ice.map")
sts, ice_map_options = xTools.get_conf_options(ice_map_file,
key_lower=False)
if sts:
return sts
_family = ice_map_options.get(self.kwargs.get("DeviceFamily"))
if not _family:
xTools.say_it("Warning. Not support Family: %s" %
self.kwargs.get("DeviceFamily"))
return 1
dev_lib = _family.get(self.kwargs.get("Device"))
if not dev_lib:
xTools.say_it("Warning. Not support %s" %
self.kwargs.get("Device"))
return 1
dev, lib = re.split("\s*,\s*", dev_lib)
self.kwargs["dev_file"] = os.path.abspath(
os.path.join(self.ice_root_path, "sbt_backend", "devices", dev))
self.kwargs["lib_file"] = xTools.win2unix(
os.path.join(self.ice_root_path, "sbt_backend", "devices", lib))
# create dir
_sbt_path = os.path.join(os.getcwd(), implmnt_path, "sbt")
for item in ("bitmap", "gui", "netlister", "packer", "placer",
"router", "simulation_netlist", "timer"):
tt = os.path.join(_sbt_path, "outputs", item)
xTools.wrap_md(tt, "ice results path")
for item in ("netlist", "sds"):
tt = os.path.join(_sbt_path, "outputs", item)
xTools.wrap_md(tt, "ice results path")
self.kwargs["sdc_translator"] = os.path.abspath(
os.path.join(self.ice_root_path,
r"sbt_backend\bin\sdc_translator.tcl"))
info_line = "%s%s-%s" % (self.kwargs["DeviceFamily"],
self.kwargs["Device"],
self.kwargs["DevicePackage"])
xTools.append_file(
os.path.join(_sbt_path, "outputs", "device_info.txt"), info_line,
False)
tool_options = self.flow_options.get("tool options", dict())
_BitmapInitRamBank = tool_options.get("BitmapInitRamBank")
if not _BitmapInitRamBank:
_BitmapInitRamBank = "1111"
self.kwargs["BitmapInitRamBank"] = _BitmapInitRamBank