예제 #1
0
def main():
	
	global mode, usr, syst,svc,abt,und,irq,fiq, abtRegister, usrRegister, svcRegister, fiqRegister,irqRegister,undRegister,systRegister 

	global ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN,ORR, RSB, RSC, SBC, SUB, TEQ, TST, ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN,ORR, RSB, RSC, SBC, SUB, TEQ, TST,COND
	global MRS, MSR , BX, CLZ, BLX2, BLX1,LDR, LDRB
	global LDRBT,LDRH,LDRSB,LDRSH,LDRT,STR,STRB,STRBT,STRH,STRTMLA,MUL,SMLAL,SMULL,UMLAL,UMULL, LDM1, LDM2, LDM3, STM1, STM2 
	global LR,PC,CPSR,SPSR
	addMode = 0
	
	usr = 0
	syst = 1
	svc = 2
	abt = 3
	und = 4
	irq = 5
	fiq = 6
	mode = usr
	LR = 14
	PC = 15     
	CPSR = 16
	SPSR = 17	

	## will add ability to pass in file name as arguement.	
	#filename = 'code/template.machine'
	#filename = 'code/instTests/adc/adc.test'
	# inits our regs	
	register = regInit()
	# inits our memory
	
	# sets the registers up
	register = setMode(mode, usr, register)
	# ganks a binary, converts to hex

	#g = g[0].strip("\n")
	#	print()
	#	print(g)
	
	Memory, register[PC] = elf.loadfile(sys.stdin.readlines()[0].strip("\n"))

	#print(hex(entry))
	#print(Memory)

	ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN,ORR, RSB, RSC, SBC, SUB, TEQ, TST = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
			# Misc Insts, Branching.

	MRS, MSR , BX, CLZ, BLX2, BLX1, BBL = 17,18,19,20,21,22,48
			# Multiplies:

	MLA,MUL,SMLAL,SMULL,UMLAL,UMULL = 23,24,25,26,27,28
			## load/store mults:
	
	LDM1, LDM2, LDM3, STM1, STM2 = 29,30,31,32,33
			# extra load/store instructions:
	
	LDR, LDRB, LDRBT,LDRH,LDRSB,LDRSH,LDRT,STR,STRB,STRBT,STRH,STRT= 34,35,36,37,38,39,40,41,42,43,44,45
	DP32BitImmediate = 0
	DPImmediateShift= 1 
	DPRegShift = 2
	MLSImmOffIndex = 3
	MLSRegOffIndex = 4
	LSImmOffIndex = 5
	LSRegOffIndex = 6
	LSScaleRegOffIndex = 7		
	LSMultiple = 8
	UND = 96
	IRREL = 10
	UNPRED = 99
	BKPT = 98
	SWI = 97
	PC = 15
	CPSR = 16
	SPSR = 17
	COND = 0
	#barrelShifter = BarrellShifter()
	#register[PC] = 0x8054
	while True:  # represents the main loop
		
		for i in range(16):
			print("R[{0}] :".format(i),hex(register[i]))
		word = fetch(Memory, register)

		addMode = BarrellShifter.determineMode(word)
		inst = Instructions.parseInstruction(word)
		
		register[PC] = register[PC] +4
		instStr = setInstString(inst)
		if inst == BKPT or inst == SWI:
			handleException(word,inst,addMode)

		else:
			if addMode == DP32BitImmediate or addMode == DPImmediateShift or addMode == DPRegShift:
				shifter_operand, shifter_carry_out, register = BarrellShifter.do_data_proc(word,addMode,inst,register)
				register = Instructions.do_dp(shifter_operand,shifter_carry_out,register,inst,word)
			
			elif addMode == MLSImmOffIndex or addMode == MLSRegOffIndex:
				address,register = BarrellShifter.do_misc_l_s(word,addMode,inst,register)
				register, Memory = Instructions.do_LS(address,Memory,register,inst,word)

			elif addMode == LSMultiple:
				start_address,end_address,register = BarrellShifter.do_l_s_mult(word,addMode,inst,register)
				Memory, register = Instructions.do_LSM(start_address,end_address,Memory,register,inst,word)
			
			elif addMode == LSImmOffIndex or addMode == LSRegOffIndex or addMode == LSScaleRegOffIndex:
				address, register = BarrellShifter.do_l_s(word,addMode,inst,register)
				register, Memory = Instructions.do_LS(address,Memory,register,inst,word)
			elif inst >22 and inst <29:
				register =  Instructions.do_multiplies(Memory,register,word,inst,addMode)
			else: 
				register = Instructions.do_misc(Memory,register,word,inst,addMode)
			print("Word: ", bin(word),". Add Mode: ", addMode, "Inst: ", instStr)