def _createWriteTransactionElement(self,
addrTableItem,
dataList,
addrOffset=0,
isFifo=False):
"""Returns a Write Request transaction element (i.e. unmasked/block write)
addrTableItem: The relevant address table item you want to perform the write transaction on.
dataList: The list of 32-bit numbers you want to write (the list size defines the write depth)
addrOffset: The offset on the address specified within the address table item, default is 0.
isFifo: False gives a normal write transaction; True gives a non-incrementing write transaction (i.e. same addr many times).
"""
for value in dataList:
if not uInt32Compatible(value):
raise ChipsException("Write transaction creation error: cannot create a write transaction with data " \
"values (" + hex(value) +") that are not valid 32-bit unsigned integers!")
typeId = IPbusHeader.TYPE_ID_WRITE
if isFifo: typeId = IPbusHeader.TYPE_ID_NON_INCR_WRITE
writeHeader = IPbusHeader.makeHeader(ChipsBusBase.IPBUS_PROTOCOL_VER,
self._getTransactionId(),
len(dataList), typeId,
IPbusHeader.INFO_CODE_REQUEST)
writeBody = [addrTableItem.getAddress() + addrOffset] + dataList
return TransactionElement.makeFromHeaderAndBody(writeHeader, writeBody)
def _createRMWBitsTransactionElement(self, addrTableItem, dataU32, addrOffset = 0):
"""Returns a Read/Modify/Write Bits Request transaction element (i.e. masked write)
addrTableItem: The relevant address table item you want to perform the RMWBits transaction on.
dataU32: The data (32 bits max, or equal in width to the bit-mask).
addrOffset: The offset on the address specified within the address table item, default is 0.
"""
if not uInt32Compatible(dataU32):
raise ChipsException("Read-Modify-Write Bits transaction creation error: cannot create a RMW-bits " \
"transaction with data values (" + hex(dataU32) +") that are not valid 32-bit " \
"unsigned integers!")
rmwHeader = IPbusHeader.makeHeader(ChipsBus.IPBUS_PROTOCOL_VER, self._getTransactionId(), 1, IPbusHeader.TYPE_ID_RMW_BITS, IPbusHeader.INFO_CODE_REQUEST)
rmwBody = [addrTableItem.getAddress() + addrOffset, \
uInt32BitFlip(addrTableItem.getMask()), \
addrTableItem.shiftDataToMask(dataU32)]
return TransactionElement.makeFromHeaderAndBody(rmwHeader, rmwBody)
def _createWriteTransactionElement(self, addrTableItem, dataList, addrOffset = 0, isFifo = False):
"""Returns a Write Request transaction element (i.e. unmasked/block write)
addrTableItem: The relevant address table item you want to perform the write transaction on.
dataList: The list of 32-bit numbers you want to write (the list size defines the write depth)
addrOffset: The offset on the address specified within the address table item, default is 0.
isFifo: False gives a normal write transaction; True gives a non-incrementing write transaction (i.e. same addr many times).
"""
for value in dataList:
if not uInt32Compatible(value):
raise ChipsException("Write transaction creation error: cannot create a write transaction with data " \
"values (" + hex(value) +") that are not valid 32-bit unsigned integers!")
typeId = IPbusHeader.TYPE_ID_WRITE
if isFifo: typeId = IPbusHeader.TYPE_ID_NON_INCR_WRITE
writeHeader = IPbusHeader.makeHeader(ChipsBusBase.IPBUS_PROTOCOL_VER, self._getTransactionId(), len(dataList), typeId, IPbusHeader.INFO_CODE_REQUEST)
writeBody = [addrTableItem.getAddress() + addrOffset] + dataList
return TransactionElement.makeFromHeaderAndBody(writeHeader, writeBody)
def _createRMWBitsTransactionElement(self, addrTableItem, dataU32, addrOffset = 0):
"""Returns a Read/Modify/Write Bits Request transaction element (i.e. masked write)
addrTableItem: The relevant address table item you want to perform the RMWBits transaction on.
dataU32: The data (32 bits max, or equal in width to the bit-mask).
addrOffset: The offset on the address specified within the address table item, default is 0.
"""
if not uInt32Compatible(dataU32):
raise ChipsException("Read-Modify-Write Bits transaction creation error: cannot create a RMW-bits " \
"transaction with data values (" + hex(dataU32) +") that are not valid 32-bit " \
"unsigned integers!")
rmwHeader = IPbusHeader.makeHeader(ChipsBus.IPBUS_PROTOCOL_VER, self._getTransactionId(), 1, IPbusHeader.TYPE_ID_RMW_BITS, IPbusHeader.INFO_CODE_REQUEST)
rmwBody = [addrTableItem.getAddress() + addrOffset, \
uInt32BitFlip(addrTableItem.getMask()), \
addrTableItem.shiftDataToMask(dataU32)]
return TransactionElement.makeFromHeaderAndBody(rmwHeader, rmwBody)
def _readAddrTable(self, addressTableFile):
"""Read in an address table from the specified file"""
file = open(addressTableFile, "r")
line = file.readline() # Get the first line
lineNum = 1
while len(line) != 0: # i.e. not the end of the file
words = line.split() # Split up the line into words by its whitespace
if len(words) != 0: # A blank line (or a line with just whitespace).
if line[0] != "*": # Not a commented line
if len(words) < 5:
raise ChipsException(
"Line "
+ str(lineNum)
+ " of file '"
+ addressTableFile
+ "' does not conform to file format expectations!"
)
try:
regName = words[0]
regAddr = int(words[1], 16)
regMask = int(words[2], 16)
regRead = int(words[3])
regWrite = int(words[4])
except Exception, err:
raise ChipsException(
"Line "
+ str(lineNum)
+ " of file '"
+ addressTableFile
+ "' does not conform to file format expectations! (Detail: "
+ str(err)
)
if regName in self.items:
raise ChipsException(
"Register '"
+ regName
+ "' is included in the file '"
+ addressTableFile
+ "' more than once!"
)
if not (uInt32Compatible(regAddr) and uInt32Compatible(regMask)):
raise ChipsException(
"Register address or mask on line "
+ str(lineNum)
+ " of file '"
+ addressTableFile
+ "' is not "
"a valid 32-bit unsigned number!"
)
if regMask == 0:
raise ChipsException(
"Register mask on line "
+ str(lineNum)
+ " of file '"
+ addressTableFile
+ "' is zero! This is not allowed!"
)
if regRead != 0 and regRead != 1:
raise ChipsException(
"Read flag on line "
+ str(lineNum)
+ " of file '"
+ addressTableFile
+ "' is not one or zero!"
)
if regWrite != 0 and regWrite != 1:
raise ChipsException(
"Write flag on line "
+ str(lineNum)
+ " of file '"
+ addressTableFile
+ "' is not one or zero!"
)
item = AddressTableItem(regName, regAddr, regMask, regRead, regWrite)
self.items[regName] = item
line = file.readline() # Get the next line and start again.
lineNum += 1
def _readAddrTable(self, addressTableFile):
'''Read in an address table from the specified file'''
file = open(addressTableFile, 'r')
line = file.readline() # Get the first line
lineNum = 1
while len(line) != 0: # i.e. not the end of the file
words = line.split(
) # Split up the line into words by its whitespace
if len(words
) != 0: # A blank line (or a line with just whitespace).
if line[0] != '*': # Not a commented line
if len(words) < 5:
raise ChipsException(
"Line " + str(lineNum) + " of file '" +
addressTableFile +
"' does not conform to file format expectations!")
try:
regName = words[0]
regAddr = int(words[1], 16)
regMask = int(words[2], 16)
regRead = int(words[3])
regWrite = int(words[4])
except Exception as err:
raise ChipsException(
"Line " + str(lineNum) + " of file '" +
addressTableFile +
"' does not conform to file format expectations! (Detail: "
+ str(err))
if regName in self.items:
raise ChipsException("Register '" + regName +
"' is included in the file '" +
addressTableFile +
"' more than once!")
if not (uInt32Compatible(regAddr)
and uInt32Compatible(regMask)):
raise ChipsException("Register address or mask on line " + str(lineNum) +
" of file '" + addressTableFile + "' is not " \
"a valid 32-bit unsigned number!")
if regMask == 0:
raise ChipsException("Register mask on line " +
str(lineNum) + " of file '" +
addressTableFile +
"' is zero! This is not allowed!")
if regRead != 0 and regRead != 1:
raise ChipsException("Read flag on line " +
str(lineNum) + " of file '" +
addressTableFile +
"' is not one or zero!")
if regWrite != 0 and regWrite != 1:
raise ChipsException("Write flag on line " +
str(lineNum) + " of file '" +
addressTableFile +
"' is not one or zero!")
item = AddressTableItem(regName, regAddr, regMask, regRead,
regWrite)
self.items[regName] = item
line = file.readline() # Get the next line and start again.
lineNum += 1
