def attachPciDevices(self):
self.ethernet = IGbE_e1000(pci_bus=0,
pci_dev=0,
pci_func=0,
InterruptLine=1,
InterruptPin=1)
self.ide = IdeController(disks=[],
pci_bus=0,
pci_dev=1,
pci_func=0,
InterruptLine=2,
InterruptPin=2)
def attachPciDevices(self):
use_virtio = False
if use_virtio:
self.virtio = PciVirtIO(pci_bus=0, pci_dev=1, pci_func=0)
else:
self.ethernet = IGbE_e1000(pci_bus=0,
pci_dev=0,
pci_func=0,
InterruptLine=1,
InterruptPin=1)
self.ide = IdeController(disks=[],
pci_bus=0,
pci_dev=1,
pci_func=0,
InterruptLine=2,
InterruptPin=2)
def attachPciDevices(self):
#self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
# InterruptLine=1, InterruptPin=1)
#self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
# InterruptLine=2, InterruptPin=2)
self.ethernet = IGbE_e1000(pci_bus=0,
pci_dev=self._num_pci_dev,
pci_func=0,
InterruptLine=self._num_pci_int_line,
InterruptPin=1)
self._num_pci_dev = self._num_pci_dev + 1
self._num_pci_int_line = self._num_pci_int_line + 1
self.ide = IdeController(disks=[],
pci_bus=0,
pci_dev=self._num_pci_dev,
pci_func=0,
InterruptLine=self._num_pci_int_line,
InterruptPin=2)
self._num_pci_dev = self._num_pci_dev + 1
self._num_pci_int_line = self._num_pci_int_line + 1
class VExpress_EMM(RealView):
mem_start_addr = '2GB'
max_mem_size = '2GB'
pci_cfg_base = 0x30000000
uart = Pl011(pio_addr=0x1c090000, int_num=37)
realview_io = RealViewCtrl(proc_id0=0x14000000,
proc_id1=0x14000000,
pio_addr=0x1C010000)
gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
local_cpu_timer = CpuLocalTimer(int_num_timer=29,
int_num_watchdog=30,
pio_addr=0x2C080000)
generic_timer = GenericTimer(int_num=29)
timer0 = Sp804(int_num0=34,
int_num1=34,
pio_addr=0x1C110000,
clock0='1MHz',
clock1='1MHz')
timer1 = Sp804(int_num0=35,
int_num1=35,
pio_addr=0x1C120000,
clock0='1MHz',
clock1='1MHz')
clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117)
kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
cf_ctrl = IdeController(disks=[],
pci_func=0,
pci_dev=0,
pci_bus=2,
io_shift=2,
ctrl_offset=2,
Command=0x1,
BAR0=0x1C1A0000,
BAR0Size='256B',
BAR1=0x1C1A0100,
BAR1Size='4096B',
BAR0LegacyIO=True,
BAR1LegacyIO=True)
pciconfig = PciConfigAll(size='256MB')
ethernet = IGbE_e1000(pci_bus=0,
pci_dev=0,
pci_func=0,
InterruptLine=1,
InterruptPin=1)
ide = IdeController(disks=[],
pci_bus=0,
pci_dev=1,
pci_func=0,
InterruptLine=2,
InterruptPin=2)
vram = SimpleMemory(range=AddrRange(0x18000000, size='32MB'),
conf_table_reported=False)
rtc = PL031(pio_addr=0x1C170000, int_num=36)
l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
aaci_fake = AmbaFake(pio_addr=0x1C040000)
lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
mmc_fake = AmbaFake(pio_addr=0x1c050000)
def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range=AddrRange('64MB'),
conf_table_reported=False)
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot_emm.arm')
cur_sys.atags_addr = 0x8000000
cur_sys.load_addr_mask = 0xfffffff
cur_sys.load_offset = 0x80000000
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.master
self.local_cpu_timer.pio = bus.master
self.hdlcd.dma = bus.slave
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, a9scu)
bridge.ranges = [
AddrRange(0x2F000000, size='16MB'),
AddrRange(0x2B000000, size='4MB'),
AddrRange(0x30000000, size='256MB'),
AddrRange(0x40000000, size='512MB'),
AddrRange(0x18000000, size='64MB'),
AddrRange(0x1C000000, size='64MB')
]
self.vgic.pio = bus.master
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.timer0.pio = bus.master
self.timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.hdlcd.pio = bus.master
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.dma = bus.slave
self.cf_ctrl.config = bus.master
self.rtc.pio = bus.master
bus.use_default_range = True
self.vram.port = bus.master
self.ide.pio = bus.master
self.ide.config = bus.master
self.ide.dma = bus.slave
self.ethernet.pio = bus.master
self.ethernet.config = bus.master
self.ethernet.dma = bus.slave
self.pciconfig.pio = bus.default
self.l2x0_fake.pio = bus.master
self.uart1_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.lan_fake.pio = bus.master
self.usb_fake.pio = bus.master
self.mmc_fake.pio = bus.master
class VExpress_ELT(RealView):
max_mem_size = '2GB'
pci_cfg_base = 0xD0000000
uart0 = Pl011(pio_addr=0xE0009000, int_num=42)
uart1 = Pl011(pio_addr=0xE000A000, int_num=43)
uart = Pl011(pio_addr=0xFF009000, int_num=121)
realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000)
gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100)
local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600)
v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000)
v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000)
elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz')
elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz')
clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown
kmi0 = Pl050(pio_addr=0xFF006000, int_num=124)
kmi1 = Pl050(pio_addr=0xFF007000, int_num=125)
elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52)
elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53)
a9scu = A9SCU(pio_addr=0xE0200000)
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
io_shift = 2, ctrl_offset = 2, Command = 0x1,
BAR0 = 0xFF01A000, BAR0Size = '256B',
BAR1 = 0xFF01A100, BAR1Size = '4096B',
BAR0LegacyIO = True, BAR1LegacyIO = True)
pciconfig = PciConfigAll()
ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
InterruptLine=1, InterruptPin=1)
ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
InterruptLine=2, InterruptPin=2)
l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff)
dmac_fake = AmbaFake(pio_addr=0xE0020000)
uart2_fake = AmbaFake(pio_addr=0xE000B000)
uart3_fake = AmbaFake(pio_addr=0xE000C000)
smc_fake = AmbaFake(pio_addr=0xEC000000)
sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0xE0010000)
aaci_fake = AmbaFake(pio_addr=0xFF004000)
elba_aaci_fake = AmbaFake(pio_addr=0xE0004000)
mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this
rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031)
spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000)
lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff)
usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff)
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.master
self.a9scu.pio = bus.master
self.local_cpu_timer.pio = bus.master
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, a9scu)
bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
AddrRange(self.l2x0_fake.pio_addr, Addr.max)]
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.uart0.pio = bus.master
self.uart1.pio = bus.master
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.v2m_timer0.pio = bus.master
self.v2m_timer1.pio = bus.master
self.elba_timer0.pio = bus.master
self.elba_timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.elba_kmi0.pio = bus.master
self.elba_kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.config = bus.master
self.cf_ctrl.dma = bus.slave
self.ide.pio = bus.master
self.ide.config = bus.master
self.ide.dma = bus.slave
self.ethernet.pio = bus.master
self.ethernet.config = bus.master
self.ethernet.dma = bus.slave
self.pciconfig.pio = bus.default
bus.use_default_range = True
self.l2x0_fake.pio = bus.master
self.dmac_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.smc_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.elba_aaci_fake.pio = bus.master
self.mmc_fake.pio = bus.master
self.rtc_fake.pio = bus.master
self.spsc_fake.pio = bus.master
self.lan_fake.pio = bus.master
self.usb_fake.pio = bus.master
class SouthBridge(SimObject):
type = 'SouthBridge'
cxx_header = "dev/x86/south_bridge.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of")
_pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
_pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave')
_cmos = Cmos(pio_addr=x86IOAddress(0x70))
_dma1 = I8237(pio_addr=x86IOAddress(0x0))
_keyboard = I8042(data_port=x86IOAddress(0x60), \
command_port=x86IOAddress(0x64))
_pit = I8254(pio_addr=x86IOAddress(0x40))
_speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
_io_apic = I82094AA(pio_addr=0xFEC00000)
pic1 = Param.I8259(_pic1, "Master PIC")
pic2 = Param.I8259(_pic2, "Slave PIC")
cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
dma1 = Param.I8237(_dma1, "The first dma controller")
keyboard = Param.I8042(_keyboard, "The keyboard controller")
pit = Param.I8254(_pit, "Programmable interval timer")
speaker = Param.PcSpeaker(_speaker, "PC speaker")
io_apic = Param.I82094AA(_io_apic, "I/O APIC")
#x86 ethernet cart
ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
InterruptLine=1, InterruptPin=1)
# IDE controller
ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
ide.BAR0 = 0x1f0
ide.BAR0LegacyIO = True
ide.BAR1 = 0x3f4
ide.BAR1Size = '3B'
ide.BAR1LegacyIO = True
ide.BAR2 = 0x170
ide.BAR2LegacyIO = True
ide.BAR3 = 0x374
ide.BAR3Size = '3B'
ide.BAR3LegacyIO = True
ide.BAR4 = 1
ide.Command = 0
ide.ProgIF = 0x80
ide.InterruptLine = 14
ide.InterruptPin = 1
ide.LegacyIOBase = x86IOAddress(0)
def attachIO(self, bus, dma_ports):
# Route interupt signals
self.int_lines = \
[X86IntLine(source=self.pic1.output, sink=self.io_apic.pin(0)),
X86IntLine(source=self.pic2.output, sink=self.pic1.pin(2)),
X86IntLine(source=self.cmos.int_pin, sink=self.pic2.pin(0)),
X86IntLine(source=self.pit.int_pin, sink=self.pic1.pin(0)),
X86IntLine(source=self.pit.int_pin, sink=self.io_apic.pin(2)),
X86IntLine(source=self.keyboard.keyboard_int_pin,
sink=self.io_apic.pin(1)),
X86IntLine(source=self.keyboard.mouse_int_pin,
sink=self.io_apic.pin(12))]
# Tell the devices about each other
self.pic1.slave = self.pic2
self.speaker.i8254 = self.pit
self.io_apic.external_int_pic = self.pic1
# Connect to the bus
self.cmos.pio = bus.master
self.dma1.pio = bus.master
self.ide.pio = bus.master
if dma_ports.count(self.ide.dma) == 0:
self.ide.dma = bus.slave
self.keyboard.pio = bus.master
self.pic1.pio = bus.master
self.pic2.pio = bus.master
self.pit.pio = bus.master
self.speaker.pio = bus.master
self.io_apic.pio = bus.master
self.io_apic.int_master = bus.slave
self.ethernet.pio = bus.master #x86 ethernet configuration
self.ethernet.dma = bus.slave #x86 ethernet configuration
