def calculate_model_area(self): #Todo: Noc area self.graph.tile.calculate_tile_area( SimConfig_path=self.SimConfig_path, default_inbuf_size=self.graph.max_inbuf_size, default_outbuf_size=self.graph.max_outbuf_size) self.global_buf = buffer(SimConfig_path=self.SimConfig_path, buf_level=1, default_buf_size=self.graph.global_buf_size) self.global_buf.calculate_buf_area() self.global_add = adder(SimConfig_path=self.SimConfig_path, bitwidth=self.graph.global_adder_bitwidth) self.global_add.calculate_adder_area() for i in range(self.total_layer_num): tile_num = self.graph.layer_tileinfo[i]['tilenum'] self.arch_area[i] = self.graph.tile.tile_area * tile_num self.arch_xbar_area[i] = self.graph.tile.tile_xbar_area * tile_num self.arch_ADC_area[i] = self.graph.tile.tile_ADC_area * tile_num self.arch_DAC_area[i] = self.graph.tile.tile_DAC_area * tile_num self.arch_digital_area[ i] = self.graph.tile.tile_digital_area * tile_num self.arch_adder_area[ i] = self.graph.tile.tile_adder_area * tile_num self.arch_shiftreg_area[ i] = self.graph.tile.tile_shiftreg_area * tile_num self.arch_iReg_area[i] = self.graph.tile.tile_iReg_area * tile_num self.arch_oReg_area[i] = self.graph.tile.tile_oReg_area * tile_num self.arch_input_demux_area[ i] = self.graph.tile.tile_input_demux_area * tile_num self.arch_output_mux_area[ i] = self.graph.tile.tile_output_mux_area * tile_num self.arch_jointmodule_area[ i] = self.graph.tile.tile_jointmodule_area * tile_num self.arch_buf_area[i] = self.graph.tile.tile_buffer_area * tile_num self.arch_pooling_area[ i] = self.graph.tile.tile_pooling_area * tile_num self.arch_total_area = sum(self.arch_area) self.arch_total_xbar_area = sum(self.arch_xbar_area) self.arch_total_ADC_area = sum(self.arch_ADC_area) self.arch_total_DAC_area = sum(self.arch_DAC_area) self.arch_total_digital_area = sum( self.arch_digital_area ) + self.global_add.adder_area * self.graph.global_adder_num self.arch_total_adder_area = sum( self.arch_adder_area ) + self.global_add.adder_area * self.graph.global_adder_num self.arch_total_shiftreg_area = sum(self.arch_shiftreg_area) self.arch_total_iReg_area = sum(self.arch_iReg_area) self.arch_total_oReg_area = sum(self.arch_oReg_area) self.arch_total_input_demux_area = sum(self.arch_input_demux_area) self.arch_total_output_mux_area = sum(self.arch_output_mux_area) self.arch_total_jointmodule_area = sum(self.arch_jointmodule_area) self.arch_total_buf_area = sum( self.arch_buf_area) + self.global_buf.buf_area self.arch_total_pooling_area = sum(self.arch_pooling_area)
def calculate_model_energy(self): #print(self.model_latency.total_buffer_r_latency) self.global_buf = buffer(SimConfig_path=self.SimConfig_path, buf_level=1, default_buf_size=self.graph.global_buf_size) self.global_buf.calculate_buf_read_power() self.global_buf.calculate_buf_write_power() self.global_add = adder(SimConfig_path=self.SimConfig_path, bitwidth=self.graph.global_adder_bitwidth) self.global_add.calculate_adder_power() for i in range(self.total_layer_num): tile_num = self.graph.layer_tileinfo[i]['tilenum'] self.arch_xbar_energy[i] = self.model_power.arch_xbar_power[ i] * self.model_latency.total_xbar_latency[i] self.arch_ADC_energy[i] = self.model_power.arch_ADC_power[ i] * self.model_latency.total_ADC_latency[i] self.arch_DAC_energy[i] = self.model_power.arch_DAC_power[ i] * self.model_latency.total_DAC_latency[i] self.arch_adder_energy[i] = self.model_power.arch_adder_power[ i] * self.model_latency.total_adder_latency[i] self.arch_shiftreg_energy[ i] = self.model_power.arch_shiftreg_power[ i] * self.model_latency.total_shiftreg_latency[i] self.arch_iReg_energy[i] = self.model_power.arch_iReg_power[ i] * self.model_latency.total_iReg_latency[i] self.arch_oReg_energy[i] = self.model_power.arch_oReg_power[ i] * self.model_latency.total_oReg_latency[i] self.arch_input_demux_energy[ i] = self.model_power.arch_input_demux_power[ i] * self.model_latency.total_input_demux_latency[i] self.arch_output_mux_energy[ i] = self.model_power.arch_output_mux_power[ i] * self.model_latency.total_output_mux_latency[i] self.arch_jointmodule_energy[ i] = self.model_power.arch_jointmodule_power[ i] * self.model_latency.total_jointmodule_latency[i] self.arch_buf_r_energy[i] = self.model_power.arch_buf_r_power[ i] * self.model_latency.total_buffer_r_latency[i] self.arch_buf_w_energy[i] = self.model_power.arch_buf_w_power[ i] * self.model_latency.total_buffer_w_latency[i] self.arch_buf_energy[ i] = self.arch_buf_r_energy[i] + self.arch_buf_w_energy[i] self.arch_pooling_energy[i] = self.model_power.arch_pooling_power[ i] * self.model_latency.total_pooling_latency[i] self.arch_digital_energy[i] = self.arch_shiftreg_energy[i]+self.arch_iReg_energy[i]+self.arch_oReg_energy[i]+\ self.arch_input_demux_energy[i]+self.arch_output_mux_energy[i]+self.arch_jointmodule_energy[i] self.arch_energy[i] = self.arch_xbar_energy[i]+self.arch_ADC_energy[i]+self.arch_DAC_energy[i]+\ self.arch_digital_energy[i]+self.arch_buf_energy[i]+self.arch_pooling_energy[i] self.arch_total_energy = sum(self.arch_energy) + self.arch_Noc_energy self.arch_total_xbar_energy = sum(self.arch_xbar_energy) self.arch_total_ADC_energy = sum(self.arch_ADC_energy) self.arch_total_DAC_energy = sum(self.arch_DAC_energy) self.arch_total_digital_energy = sum(self.arch_digital_energy)+\ self.global_add.adder_power*self.graph.global_adder_num*self.global_add.adder_latency self.arch_total_adder_energy = sum(self.arch_adder_energy)+\ self.global_add.adder_power*self.graph.global_adder_num*self.global_add.adder_latency self.arch_total_shiftreg_energy = sum(self.arch_shiftreg_energy) self.arch_total_iReg_energy = sum(self.arch_iReg_energy) self.arch_total_input_demux_energy = sum(self.arch_input_demux_energy) self.arch_total_output_mux_energy = sum(self.arch_output_mux_energy) self.arch_total_jointmodule_energy = sum(self.arch_jointmodule_energy) self.arch_total_buf_energy = sum(self.arch_buf_energy) + self.global_buf.buf_rpower*1e-3*self.global_buf.buf_rlatency \ + self.global_buf.buf_wpower*1e-3*self.global_buf.buf_wlatency self.arch_total_buf_r_energy = sum( self.arch_buf_r_energy ) + self.global_buf.buf_rpower * 1e-3 * self.global_buf.buf_rlatency self.arch_total_buf_w_energy = sum( self.arch_buf_w_energy ) + self.global_buf.buf_wpower * 1e-3 * self.global_buf.buf_wlatency self.arch_total_pooling_energy = sum(self.arch_pooling_energy)
def __init__(self, SimConfig_path): crossbar.__init__(self, SimConfig_path) DAC.__init__(self, SimConfig_path) ADC.__init__(self, SimConfig_path) PE_config = cp.ConfigParser() PE_config.read(SimConfig_path, encoding='UTF-8') self.sub_position = 0 __xbar_polarity = int( PE_config.get('Process element level', 'Xbar_Polarity')) # self.PE_multiplex_xbar_num = list( # map(int, PE_config.get('Process element level', 'Multiplex_Xbar_Num').split(','))) if __xbar_polarity == 1: self.PE_multiplex_xbar_num = [1, 1] else: assert __xbar_polarity == 2, "Crossbar polarity must be 1 or 2" self.PE_multiplex_xbar_num = [1, 2] self.sub_position = int( PE_config.get('Process element level', 'Sub_Position')) self.group_num = int( PE_config.get('Process element level', 'Group_Num')) if self.group_num == 0: self.group_num = 1 self.num_occupied_group = 0 self.PE_xbar_num = self.group_num * self.PE_multiplex_xbar_num[ 0] * self.PE_multiplex_xbar_num[1] # self.polarity = PE_config.get('Algorithm Configuration', 'Weight_Polarity') # if self.polarity == 2: # assert self.PE_xbar_num[1]%2 == 0 self.PE_simulation_level = int( PE_config.get('Algorithm Configuration', 'Simulation_Level')) self.PE_xbar_list = [] self.PE_xbar_enable = [] for i in range(self.group_num): self.PE_xbar_list.append([]) self.PE_xbar_enable.append([]) for j in range(self.PE_multiplex_xbar_num[0] * self.PE_multiplex_xbar_num[1]): __xbar = crossbar(SimConfig_path) self.PE_xbar_list[i].append(__xbar) self.PE_xbar_enable[i].append(0) self.PE_group_ADC_num = int( PE_config.get('Process element level', 'ADC_Num')) self.PE_group_DAC_num = int( PE_config.get('Process element level', 'DAC_Num')) self.PE_ADC_num = 0 self.PE_DAC_num = 0 self.input_demux = 0 self.input_demux_power = 0 self.input_demux_area = 0 self.output_mux = 0 self.output_mux_power = 0 self.output_mux_area = 0 self.calculate_ADC_num() self.calculate_DAC_num() self.PE_adder = adder(SimConfig_path) self.PE_adder_num = 0 self.PE_shiftreg = shiftreg(SimConfig_path) self.PE_iReg = reg(SimConfig_path) self.PE_oReg = reg(SimConfig_path) self.PE_utilization = 0 self.PE_max_occupied_column = 0 self.PE_area = 0 self.PE_xbar_area = 0 self.PE_ADC_area = 0 self.PE_DAC_area = 0 self.PE_adder_area = 0 self.PE_shiftreg_area = 0 self.PE_iReg_area = 0 self.PE_oReg_area = 0 self.PE_input_demux_area = 0 self.PE_output_mux_area = 0 self.PE_digital_area = 0 self.PE_inbuf_area = 0 self.PE_read_power = 0 self.PE_xbar_read_power = 0 self.PE_ADC_read_power = 0 self.PE_DAC_read_power = 0 self.PE_adder_read_power = 0 self.PE_shiftreg_read_power = 0 self.PE_iReg_read_power = 0 self.PE_oReg_read_power = 0 self.input_demux_read_power = 0 self.output_mux_read_power = 0 self.PE_digital_read_power = 0 self.PE_inbuf_read_rpower = 0 self.PE_inbuf_read_wpower = 0 self.PE_inbuf_read_power = 0 self.PE_write_power = 0 self.PE_xbar_write_power = 0 self.PE_ADC_write_power = 0 self.PE_DAC_write_power = 0 self.PE_adder_write_power = 0 self.PE_shiftreg_write_power = 0 self.PE_iReg_write_power = 0 self.input_demux_write_power = 0 self.output_mux_write_power = 0 self.PE_digital_write_power = 0 self.PE_read_latency = 0 self.PE_xbar_read_latency = 0 self.PE_ADC_read_latency = 0 self.PE_DAC_read_latency = 0 self.PE_adder_read_latency = 0 self.PE_shiftreg_read_latency = 0 self.PE_iReg_read_latency = 0 self.input_demux_read_latency = 0 self.output_mux_read_latency = 0 self.PE_digital_read_latency = 0 self.PE_write_latency = 0 self.PE_xbar_write_latency = 0 self.PE_ADC_write_latency = 0 self.PE_DAC_write_latency = 0 self.PE_adder_write_latency = 0 self.PE_shiftreg_write_latency = 0 self.PE_iReg_write_latency = 0 self.input_demux_write_latency = 0 self.output_mux_write_latency = 0 self.PE_digital_write_latency = 0 self.PE_read_energy = 0 self.PE_xbar_read_energy = 0 self.PE_ADC_read_energy = 0 self.PE_DAC_read_energy = 0 self.PE_adder_read_energy = 0 self.PE_shiftreg_read_energy = 0 self.PE_iReg_read_energy = 0 self.input_demux_read_energy = 0 self.output_mux_read_energy = 0 self.PE_digital_read_energy = 0 self.PE_write_energy = 0 self.PE_xbar_write_energy = 0 self.PE_ADC_write_energy = 0 self.PE_DAC_write_energy = 0 self.PE_adder_write_energy = 0 self.PE_shiftreg_write_energy = 0 self.PE_iReg_write_energy = 0 self.input_demux_write_energy = 0 self.output_mux_write_energy = 0 self.PE_digital_write_energy = 0 self.calculate_inter_PE_connection()
def calculate_model_area(self): #Todo: Noc area self.graph.tile.calculate_tile_area( SimConfig_path=self.SimConfig_path, default_inbuf_size=self.graph.max_inbuf_size, default_outbuf_size=self.graph.max_outbuf_size) self.global_buf = buffer(SimConfig_path=self.SimConfig_path, buf_level=1, default_buf_size=self.graph.global_buf_size) self.global_buf.calculate_buf_area() self.global_add = adder(SimConfig_path=self.SimConfig_path, bitwidth=self.graph.global_adder_bitwidth) self.global_add.calculate_adder_area() self.tile = tile(SimConfig_path=self.SimConfig_path) self.tile_xbar_num = self.tile.tile_PE_total_num * self.tile.group_num * self.tile.xbar_column * self.tile.xbar_row self.tile_DAC_num = self.tile.tile_PE_total_num * self.tile.group_num * self.tile.xbar_row self.tile_ADC_num = self.tile.tile_PE_total_num * self.tile.group_num * self.tile.xbar_column total_tile_num = 0 used_total_xbar_num = 0 used_total_DAC_num = 0 used_total_ADC_num = 0 # not the real DAC/ADC num, but it reflects the DAC/ADC num for i in range(self.total_layer_num): layer_dict = self.NetStruct[i][0][0] tile_num = self.graph.layer_tileinfo[i]['tilenum'] self.arch_area[i] = self.graph.tile.tile_area * tile_num self.arch_xbar_area[i] = self.graph.tile.tile_xbar_area * tile_num self.arch_ADC_area[i] = self.graph.tile.tile_ADC_area * tile_num self.arch_DAC_area[i] = self.graph.tile.tile_DAC_area * tile_num self.arch_digital_area[ i] = self.graph.tile.tile_digital_area * tile_num self.arch_adder_area[ i] = self.graph.tile.tile_adder_area * tile_num self.arch_shiftreg_area[ i] = self.graph.tile.tile_shiftreg_area * tile_num self.arch_iReg_area[i] = self.graph.tile.tile_iReg_area * tile_num self.arch_oReg_area[i] = self.graph.tile.tile_oReg_area * tile_num self.arch_input_demux_area[ i] = self.graph.tile.tile_input_demux_area * tile_num self.arch_output_mux_area[ i] = self.graph.tile.tile_output_mux_area * tile_num self.arch_jointmodule_area[ i] = self.graph.tile.tile_jointmodule_area * tile_num self.arch_buf_area[i] = self.graph.tile.tile_buffer_area * tile_num self.arch_pooling_area[ i] = self.graph.tile.tile_pooling_area * tile_num if self.graph.layer_tileinfo[i]['type'] == 'conv': # only consider the utilization rate of conv layer and fc layer total_tile_num += tile_num used_xbar_num = self.graph.layer_tileinfo[i][ 'x_width'] * self.graph.layer_tileinfo[i]['y_height'] used_DAC_num = self.graph.layer_tileinfo[i][ 'y_height'] * self.graph.layer_tileinfo[i][ 'weight_precision'] * math.ceil( int(layer_dict['Outputchannel']) / self.tile.xbar_column) used_ADC_num = self.graph.layer_tileinfo[i][ 'x_width'] * self.graph.layer_tileinfo[i]['my'] self.arch_xbar_utilization[i] = used_xbar_num / ( tile_num * self.tile_xbar_num) self.arch_DAC_utilization[i] = used_DAC_num / ( tile_num * self.tile_DAC_num) self.arch_ADC_utilization[i] = used_ADC_num / ( tile_num * self.tile_ADC_num) used_total_xbar_num += used_xbar_num used_total_DAC_num += used_DAC_num used_total_ADC_num += used_ADC_num if self.graph.layer_tileinfo[i]['type'] == 'fc': # only consider the utilization rate of conv layer and fc layer total_tile_num += tile_num used_xbar_num = self.graph.layer_tileinfo[i][ 'x_width'] * self.graph.layer_tileinfo[i]['y_height'] used_DAC_num = self.graph.layer_tileinfo[i][ 'y_height'] * self.graph.layer_tileinfo[i][ 'weight_precision'] * math.ceil( int(layer_dict['Outfeature']) / self.tile.xbar_column) used_ADC_num = self.graph.layer_tileinfo[i][ 'x_width'] * self.graph.layer_tileinfo[i]['my'] self.arch_xbar_utilization[i] = used_xbar_num / ( tile_num * self.tile_xbar_num) self.arch_DAC_utilization[i] = used_DAC_num / ( tile_num * self.tile_DAC_num) self.arch_ADC_utilization[i] = used_ADC_num / ( tile_num * self.tile_ADC_num) used_total_xbar_num += used_xbar_num used_total_DAC_num += used_DAC_num used_total_ADC_num += used_ADC_num self.arch_total_area = sum(self.arch_area) self.arch_total_xbar_area = sum(self.arch_xbar_area) self.arch_total_ADC_area = sum(self.arch_ADC_area) self.arch_total_DAC_area = sum(self.arch_DAC_area) self.arch_total_digital_area = sum( self.arch_digital_area ) + self.global_add.adder_area * self.graph.global_adder_num self.arch_total_adder_area = sum( self.arch_adder_area ) + self.global_add.adder_area * self.graph.global_adder_num self.arch_total_shiftreg_area = sum(self.arch_shiftreg_area) self.arch_total_iReg_area = sum(self.arch_iReg_area) self.arch_total_oReg_area = sum(self.arch_oReg_area) self.arch_total_input_demux_area = sum(self.arch_input_demux_area) self.arch_total_output_mux_area = sum(self.arch_output_mux_area) self.arch_total_jointmodule_area = sum(self.arch_jointmodule_area) self.arch_total_buf_area = sum( self.arch_buf_area) + self.global_buf.buf_area self.arch_total_pooling_area = sum(self.arch_pooling_area) self.arch_total_xbar_utilization = used_total_xbar_num / ( total_tile_num * self.tile_xbar_num) self.arch_total_DAC_utilization = used_total_DAC_num / ( total_tile_num * self.tile_DAC_num) self.arch_total_ADC_utilization = used_total_ADC_num / ( total_tile_num * self.tile_ADC_num)
def calculate_model_power(self): self.global_buf = buffer(SimConfig_path=self.SimConfig_path, buf_level=1, default_buf_size=self.graph.global_buf_size) self.global_buf.calculate_buf_read_power() self.global_buf.calculate_buf_write_power() self.global_add = adder(SimConfig_path=self.SimConfig_path, bitwidth=self.graph.global_adder_bitwidth) self.global_add.calculate_adder_power() for i in range(self.total_layer_num): tile_num = self.graph.layer_tileinfo[i]['tilenum'] max_column = self.graph.layer_tileinfo[i]['max_column'] max_row = self.graph.layer_tileinfo[i]['max_row'] max_PE = self.graph.layer_tileinfo[i]['max_PE'] max_group = self.graph.layer_tileinfo[i]['max_group'] layer_type = self.graph.net[i][0][0]['type'] self.graph.tile.calculate_tile_read_power_fast( max_column=max_column, max_row=max_row, max_PE=max_PE, max_group=max_group, layer_type=layer_type, SimConfig_path=self.SimConfig_path, default_inbuf_size=self.graph.max_inbuf_size, default_outbuf_size=self.graph.max_outbuf_size) self.arch_power[i] = self.graph.tile.tile_read_power * tile_num self.arch_xbar_power[ i] = self.graph.tile.tile_xbar_read_power * tile_num self.arch_ADC_power[ i] = self.graph.tile.tile_ADC_read_power * tile_num self.arch_DAC_power[ i] = self.graph.tile.tile_DAC_read_power * tile_num self.arch_digital_power[ i] = self.graph.tile.tile_digital_read_power * tile_num self.arch_adder_power[ i] = self.graph.tile.tile_adder_read_power * tile_num self.arch_shiftreg_power[ i] = self.graph.tile.tile_shiftreg_read_power * tile_num self.arch_iReg_power[ i] = self.graph.tile.tile_iReg_read_power * tile_num self.arch_oReg_power[ i] = self.graph.tile.tile_oReg_read_power * tile_num self.arch_input_demux_power[ i] = self.graph.tile.tile_input_demux_read_power * tile_num self.arch_output_mux_power[ i] = self.graph.tile.tile_output_mux_read_power * tile_num self.arch_jointmodule_power[ i] = self.graph.tile.tile_jointmodule_read_power * tile_num self.arch_buf_power[ i] = self.graph.tile.tile_buffer_read_power * tile_num self.arch_buf_r_power[ i] = self.graph.tile.tile_buffer_r_read_power * tile_num self.arch_buf_w_power[ i] = self.graph.tile.tile_buffer_w_read_power * tile_num self.arch_pooling_power[ i] = self.graph.tile.tile_pooling_read_power * tile_num self.arch_total_power = sum(self.arch_power) self.arch_total_xbar_power = sum(self.arch_xbar_power) self.arch_total_ADC_power = sum(self.arch_ADC_power) self.arch_total_DAC_power = sum(self.arch_DAC_power) self.arch_total_digital_power = sum( self.arch_digital_power ) + self.global_add.adder_power * self.graph.global_adder_num self.arch_total_adder_power = sum( self.arch_adder_power ) + self.global_add.adder_power * self.graph.global_adder_num self.arch_total_shiftreg_power = sum(self.arch_shiftreg_power) self.arch_total_iReg_power = sum(self.arch_iReg_power) self.arch_total_oReg_power = sum(self.arch_oReg_power) self.arch_total_input_demux_power = sum(self.arch_input_demux_power) self.arch_total_output_mux_power = sum(self.arch_output_mux_power) self.arch_total_jointmodule_power = sum(self.arch_jointmodule_power) self.arch_total_buf_power = sum(self.arch_buf_power) + ( self.global_buf.buf_wpower + self.global_buf.buf_rpower) * 1e-3 self.arch_total_buf_r_power = sum( self.arch_buf_r_power) + self.global_buf.buf_rpower * 1e-3 self.arch_total_buf_w_power = sum( self.arch_buf_w_power) + self.global_buf.buf_wpower * 1e-3 self.arch_total_pooling_power = sum(self.arch_pooling_power)
def __init__(self, SimConfig_path): # layer_num is a list with the size of 1xPE_num ProcessElement.__init__(self, SimConfig_path) tile_config = cp.ConfigParser() tile_config.read(SimConfig_path, encoding='UTF-8') self.tile_PE_num = list( map(int, tile_config.get('Tile level', 'PE_Num').split(','))) if self.tile_PE_num[0] == 0: self.tile_PE_num[0] = 4 self.tile_PE_num[1] = 4 assert self.tile_PE_num[0] > 0, "PE number in one PE < 0" assert self.tile_PE_num[1] > 0, "PE number in one PE < 0" self.tile_PE_total_num = self.tile_PE_num[0] * self.tile_PE_num[1] self.tile_simulation_level = int( tile_config.get('Algorithm Configuration', 'Simulation_Level')) self.tile_PE_list = [] self.tile_PE_enable = [] for i in range(self.tile_PE_num[0]): self.tile_PE_list.append([]) self.tile_PE_enable.append([]) for j in range(self.tile_PE_num[1]): __PE = ProcessElement(SimConfig_path) self.tile_PE_list[i].append(__PE) self.tile_PE_enable[i].append(0) self.layer_type = 'conv' self.tile_layer_num = 0 self.tile_activation_precision = 0 self.tile_sliding_times = 0 self.tile_adder_num = 0 self.tile_shiftreg_num = 0 self.tile_jointmodule_num = 0 self.tile_adder = adder(SimConfig_path) self.tile_shiftreg = shiftreg(SimConfig_path) self.tile_iReg = reg(SimConfig_path) self.tile_oReg = reg(SimConfig_path) self.tile_jointmodule = JointModule(SimConfig_path) self.tile_buffer = buffer(SimConfig_path) self.tile_pooling = Pooling(SimConfig_path) self.tile_utilization = 0 self.num_occupied_PE = 0 self.tile_area = 0 self.tile_xbar_area = 0 self.tile_ADC_area = 0 self.tile_DAC_area = 0 self.tile_digital_area = 0 self.tile_adder_area = 0 self.tile_shiftreg_area = 0 self.tile_iReg_area = 0 self.tile_oReg_area = 0 self.tile_input_demux_area = 0 self.tile_output_mux_area = 0 self.tile_jointmodule_area = 0 self.tile_pooling_area = 0 self.tile_buffer_area = 0 self.tile_read_power = 0 self.tile_xbar_read_power = 0 self.tile_ADC_read_power = 0 self.tile_DAC_read_power = 0 self.tile_digital_read_power = 0 self.tile_adder_read_power = 0 self.tile_shiftreg_read_power = 0 self.tile_iReg_read_power = 0 self.tile_oReg_read_power = 0 self.tile_input_demux_read_power = 0 self.tile_output_mux_read_power = 0 self.tile_jointmodule_read_power = 0 self.tile_pooling_read_power = 0 self.tile_buffer_read_power = 0 self.tile_buffer_r_read_power = 0 self.tile_buffer_w_read_power = 0 self.tile_write_power = 0 self.tile_xbar_write_power = 0 self.tile_ADC_write_power = 0 self.tile_DAC_write_power = 0 self.tile_digital_write_power = 0 self.tile_adder_write_power = 0 self.tile_shiftreg_write_power = 0 self.tile_iReg_write_power = 0 self.tile_input_demux_write_power = 0 self.tile_output_mux_write_power = 0 self.tile_jointmodule_write_power = 0 self.tile_read_latency = 0 self.tile_xbar_read_latency = 0 self.tile_ADC_read_latency = 0 self.tile_DAC_read_latency = 0 self.tile_digital_read_latency = 0 self.tile_adder_read_latency = 0 self.tile_shiftreg_read_latency = 0 self.tile_iReg_read_latency = 0 self.tile_input_demux_read_latency = 0 self.tile_output_mux_read_latency = 0 self.tile_jointmodule_read_latency = 0 # self.tile_layer_read_latency = {0:0} self.tile_write_latency = 0 self.tile_xbar_write_latency = 0 self.tile_ADC_write_latency = 0 self.tile_DAC_write_latency = 0 self.tile_digital_write_latency = 0 self.tile_adder_write_latency = 0 self.tile_shiftreg_write_latency = 0 self.tile_iReg_write_latency = 0 self.tile_input_demux_write_latency = 0 self.tile_output_mux_write_latency = 0 self.tile_jointmodule_write_latency = 0 # self.tile_layer_write_latency = {0:0} self.tile_read_energy = 0 self.tile_xbar_read_energy = 0 self.tile_ADC_read_energy = 0 self.tile_DAC_read_energy = 0 self.tile_digital_read_energy = 0 self.tile_adder_read_energy = 0 self.tile_shiftreg_read_energy = 0 self.tile_iReg_read_energy = 0 self.tile_input_demux_read_energy = 0 self.tile_output_mux_read_energy = 0 self.tile_jointmodule_read_energy = 0 self.tile_write_energy = 0 self.tile_xbar_write_energy = 0 self.tile_ADC_write_energy = 0 self.tile_DAC_write_energy = 0 self.tile_digital_write_energy = 0 self.tile_adder_write_energy = 0 self.tile_shiftreg_write_energy = 0 self.tile_iReg_write_energy = 0 self.tile_input_demux_write_energy = 0 self.tile_output_mux_write_energy = 0 self.tile_jointmodule_write_energy = 0 # print("tile configuration is loaded") self.calculate_intra_PE_connection()