예제 #1
0
def test_connect():

  m = TwoQueues( 8 )
  m.elaborate()
  verify_signals( m.get_inports(),  [('in_.msg', 8), ('in_.val', 1), ('out.rdy', 1),
                                     ('clk', 1), ('reset', 1)] )
  verify_signals( m.get_outports(), [('out.msg', 8), ('out.val', 1), ('in_.rdy', 1)] )
  verify_signals( m.get_wires(),    [] )
  verify_submodules( m.get_submodules() , [m.q1, m.q2] )
  verify_edges( m.get_connections(), [ ConnectionEdge( m.clk,        m.q1.clk     ),
                                       ConnectionEdge( m.reset,      m.q1.reset   ),
                                       ConnectionEdge( m.clk,        m.q2.clk     ),
                                       ConnectionEdge( m.reset,      m.q2.reset   ),

                                       ConnectionEdge( m.in_.msg,    m.q1.enq.msg ),
                                       ConnectionEdge( m.in_.val,    m.q1.enq.val ),
                                       ConnectionEdge( m.q1.enq.rdy, m.in_.rdy    ),

                                       ConnectionEdge( m.q1.deq.msg, m.q2.enq.msg ),
                                       ConnectionEdge( m.q1.deq.val, m.q2.enq.val ),
                                       ConnectionEdge( m.q2.enq.rdy, m.q1.deq.rdy ),

                                       ConnectionEdge( m.q2.deq.msg, m.out.msg    ),
                                       ConnectionEdge( m.q2.deq.val, m.out.val    ),
                                       ConnectionEdge( m.out.rdy,    m.q2.deq.rdy ),
                                     ] )
예제 #2
0
def test_connect():

    m = TwoQueues(8)
    m.elaborate()
    verify_signals(m.get_inports(), [('in_.msg', 8), ('in_.val', 1),
                                     ('out.rdy', 1), ('clk', 1), ('reset', 1)])
    verify_signals(m.get_outports(), [('out.msg', 8), ('out.val', 1),
                                      ('in_.rdy', 1)])
    verify_signals(m.get_wires(), [])
    verify_submodules(m.get_submodules(), [m.q1, m.q2])
    verify_edges(m.get_connections(), [
        ConnectionEdge(m.clk, m.q1.clk),
        ConnectionEdge(m.reset, m.q1.reset),
        ConnectionEdge(m.clk, m.q2.clk),
        ConnectionEdge(m.reset, m.q2.reset),
        ConnectionEdge(m.in_.msg, m.q1.enq.msg),
        ConnectionEdge(m.in_.val, m.q1.enq.val),
        ConnectionEdge(m.q1.enq.rdy, m.in_.rdy),
        ConnectionEdge(m.q1.deq.msg, m.q2.enq.msg),
        ConnectionEdge(m.q1.deq.val, m.q2.enq.val),
        ConnectionEdge(m.q2.enq.rdy, m.q1.deq.rdy),
        ConnectionEdge(m.q2.deq.msg, m.out.msg),
        ConnectionEdge(m.q2.deq.val, m.out.val),
        ConnectionEdge(m.out.rdy, m.q2.deq.rdy),
    ])
예제 #3
0
def test_elaboration():

  m = PortBundleQueue( 8 )
  m.elaborate()

  verify_signals( m.enq.get_ports(),[('enq.msg', 8), ('enq.val', 1), ('enq.rdy', 1),] )
  verify_signals( m.deq.get_ports(),[('deq.msg', 8), ('deq.val', 1), ('deq.rdy', 1),] )

  verify_signals( m.get_inports(),  [('enq.msg', 8), ('enq.val', 1), ('deq.rdy', 1),
                                     ('clk', 1), ('reset', 1)] )
  verify_signals( m.get_outports(), [('deq.msg', 8), ('deq.val', 1), ('enq.rdy', 1)] )
  verify_signals( m.get_wires(),    [('full', 1), ('wen', 1 )] )
  verify_submodules( m.get_submodules() , [] )
  verify_edges( m.get_connections(), [] )
예제 #4
0
def test_elaboration():

    m = PortBundleQueue(8)
    m.elaborate()

    verify_signals(m.enq.get_ports(), [
        ('enq.msg', 8),
        ('enq.val', 1),
        ('enq.rdy', 1),
    ])
    verify_signals(m.deq.get_ports(), [
        ('deq.msg', 8),
        ('deq.val', 1),
        ('deq.rdy', 1),
    ])

    verify_signals(m.get_inports(), [('enq.msg', 8), ('enq.val', 1),
                                     ('deq.rdy', 1), ('clk', 1), ('reset', 1)])
    verify_signals(m.get_outports(), [('deq.msg', 8), ('deq.val', 1),
                                      ('enq.rdy', 1)])
    verify_signals(m.get_wires(), [('full', 1), ('wen', 1)])
    verify_submodules(m.get_submodules(), [])
    verify_edges(m.get_connections(), [])