useDefaultHost="False") # Configure physical interface. hPortTxCopperInterface = stc.create("EthernetCopper", under=hPortTx) # Attach ports. # Connect to a chassis print("Connecting ", szChassisIp) stc.connect(szChassisIp) # Reserve print("Reserving {0}/{1}/{2} and {3}/{4}/{5}".format(szChassisIp, iTxSlot, iTxPort, szChassisIp, iRxSlot, iRxPort)) stc.reserve("{0}/{1}/{2} {3}/{4}/{5}".format(szChassisIp, iTxSlot, iTxPort, szChassisIp, iRxSlot, iRxPort)) # Create the mapping between the physical ports and their logical # representation in the test configuration. print("Set up port mappings") stc.perform("SetupPortMappings") # Apply the configuration. print("Apply configuration") stc.apply() # Retrieve the generator and analyzer objects. hGenerator = stc.get(hPortTx, "children-Generator") hAnalyzer = stc.get(hPortRx, "children-Analyzer") # Create a stream block.
print "Creating ports ..." hPortTx = stc.create("port", under=hProject, location="//%s/%s/%s" % (szChassisIp, iTxSlot, iTxPort), useDefaultHost="False") hPortRx = stc.create("port", under=hProject, location="//%s/%s/%s" % (szChassisIp, iRxSlot, iRxPort), useDefaultHost="False") # Configure physical interface. hPortTxCopperInterface = stc.create("EthernetCopper", under=hPortTx) # Attach ports. # Connect to a chassis print "Connecting ", szChassisIp stc.connect(szChassisIp) # Reserve print "Reserving %s/%s/%s and %s/%s/%s" % (szChassisIp, iTxSlot, iTxPort, szChassisIp, iRxSlot, iRxPort) stc.reserve("%s/%s/%s %s/%s/%s" % (szChassisIp, iTxSlot, iTxPort, szChassisIp, iRxSlot, iRxPort)) # Create the mapping between the physical ports and their logical # representation in the test configuration. print "Set up port mappings" stc.perform("SetupPortMappings") # Apply the configuration. print "Apply configuration" stc.apply() # Retrieve the generator and analyzer objects. hGenerator = stc.get(hPortTx, "children-Generator") hAnalyzer = stc.get(hPortRx, "children-Analyzer") # Create a stream block.
location="//%s/%s/%s" % (szChassisIp, iRxSlot, iRxPort), useDefaultHost="False") # Configure physical interface. hPortTxCopperInterface = stc.create("EthernetCopper", under=hPortTx) # Attach ports. # Connect to a chassis print "Connecting ", szChassisIp stc.connect(szChassisIp) # Reserve print "Reserving %s/%s/%s and %s/%s/%s" % (szChassisIp, iTxSlot, iTxPort, szChassisIp, iRxSlot, iRxPort) stc.reserve("%s/%s/%s %s/%s/%s" % (szChassisIp, iTxSlot, iTxPort, szChassisIp, iRxSlot, iRxPort)) # Create the mapping between the physical ports and their logical # representation in the test configuration. print "Set up port mappings" stc.perform("SetupPortMappings") # Apply the configuration. print "Apply configuration" stc.apply() # Retrieve the generator and analyzer objects. hGenerator = stc.get(hPortTx, "children-Generator") hAnalyzer = stc.get(hPortRx, "children-Analyzer") # Create a stream block.
print("Creating ports ...") hPortTx = stc.create("port", under=hProject, location="//{0}/{1}/{2}".format(szChassisIp, iTxSlot, iTxPort), useDefaultHost="False") hPortRx = stc.create("port", under=hProject, location="//{0}/{1}/{2}".format(szChassisIp, iRxSlot, iRxPort), useDefaultHost="False") # Configure physical interface. hPortTxCopperInterface = stc.create("EthernetCopper", under=hPortTx) # Attach ports. # Connect to a chassis print("Connecting ", szChassisIp) stc.connect(szChassisIp) # Reserve print("Reserving {0}/{1}/{2} and {3}/{4}/{5}".format(szChassisIp, iTxSlot, iTxPort, szChassisIp, iRxSlot, iRxPort)) stc.reserve("{0}/{1}/{2} {3}/{4}/{5}".format(szChassisIp, iTxSlot, iTxPort, szChassisIp, iRxSlot, iRxPort)) # Create the mapping between the physical ports and their logical # representation in the test configuration. print("Set up port mappings") stc.perform("SetupPortMappings") # Apply the configuration. print("Apply configuration") stc.apply() # Retrieve the generator and analyzer objects. hGenerator = stc.get(hPortTx, "children-Generator") hAnalyzer = stc.get(hPortRx, "children-Analyzer") # Create a stream block.