def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
# Set a width of 32 bytes (256-bits), which is four times that
# of the default bus. The clock of the CPU is inherited by
# default.
self.toL2Bus = CoherentXBar(width = 256)
self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
self.toL2Bus.master = self.l2cache.cpu_side
self._cached_ports = ['l2cache.mem_side']
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
if buildEnv['TARGET_ISA'] in ['arm']:
self.itb_walker_cache_bus = CoherentXBar()
self.dtb_walker_cache_bus = CoherentXBar()
self.itb_walker_cache_bus.master = iwc.cpu_side
self.dtb_walker_cache_bus.master = dwc.cpu_side
self.itb.walker.port = self.itb_walker_cache_bus.slave
self.dtb.walker.port = self.dtb_walker_cache_bus.slave
self.istage2_mmu.stage2_tlb.walker.port = self.itb_walker_cache_bus.slave
self.dstage2_mmu.stage2_tlb.walker.port = self.dtb_walker_cache_bus.slave
else:
self.itb.walker.port = iwc.cpu_side
self.dtb.walker.port = dwc.cpu_side
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
else:
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
if buildEnv['TARGET_ISA'] in ['arm']:
self._cached_ports += ["istage2_mmu.stage2_tlb.walker.port", \
"dstage2_mmu.stage2_tlb.walker.port"]
# Checker doesn't need its own tlb caches because it does
# functional accesses only
if self.checker != NULL:
self._cached_ports += ["checker.itb.walker.port", \
"checker.dtb.walker.port"]
if buildEnv['TARGET_ISA'] in ['arm']:
self._cached_ports += ["checker.istage2_mmu.stage2_tlb.walker.port", \
"checker.dstage2_mmu.stage2_tlb.walker.port"]