class _Module_1(Circuit):
name = "top"
IO = ['I', In(ST_SSeq(4, ST_Int(8, False)).magma_repr()),'O', Out(ST_SSeq(4, ST_Int(8, False)).magma_repr())] + ClockInterface(has_ce=False,has_reset=False) + valid_ports
st_in_t = [ST_SSeq(4, ST_Int(8, False))]
st_out_t = ST_SSeq(4, ST_Int(8, False))
binary_op = False
@classmethod
def definition(cls):
n1 = DefineFIFO(ST_SSeq(4, ST_Int(8, False)), 1, has_valid=True)()
wire(cls.I, n1.I)
wire(cls.valid_up, n1.valid_up)
n13 = DefineMap_S(4, Module_0(),True)()
wire(n1.O, n13.I)
wire(n1.valid_down, n13.valid_up)
n14 = DefineFIFO(ST_SSeq(4, ST_Int(8, False)), 1, has_valid=True)()
wire(n13.O, n14.I)
wire(n13.valid_down, n14.valid_up)
n15 = DefineFIFO(ST_SSeq(4, ST_Int(8, False)), 1, has_valid=True)()
wire(n14.O, n15.I)
wire(n14.valid_down, n15.valid_up)
n16 = DefineFIFO(ST_SSeq(4, ST_Int(8, False)), 1, has_valid=True)()
wire(n15.O, n16.I)
wire(n15.valid_down, n16.valid_up)
wire(n16.O, cls.O)
wire(n16.valid_down, cls.valid_down)
return _Module_1
Main = Module_1
fault_helpers.compile(Main(), "v./home/durst/dev/embeddedHaskellAetherling//test/no_bench/magma_examples/if_lt/if_lt_4 % 1thr.py")
ST_SSeq(4, ST_Int(8, False)),
has_valid=True)()
wire(n2.O, n3.I)
wire(n2.valid_down, n3.valid_up)
n4 = DefineUnpartition_S(1, 4, ST_Int(8, False), has_valid=True)()
wire(n3.O, n4.I)
wire(n3.valid_down, n4.valid_up)
n5 = DefineDown_S(4, 0, ST_Int(8, False), has_valid=True)()
wire(n4.O, n5.I)
wire(n4.valid_down, n5.valid_up)
n6 = DefineFIFO(ST_SSeq(1, ST_Int(8, False)), 1, has_valid=True)()
wire(n5.O, n6.I)
wire(n5.valid_down, n6.valid_up)
n7 = DefineFIFO(ST_SSeq(1, ST_Int(8, False)), 1, has_valid=True)()
wire(n6.O, n7.I)
wire(n6.valid_down, n7.valid_up)
n8 = DefineFIFO(ST_SSeq(1, ST_Int(8, False)), 1, has_valid=True)()
wire(n7.O, n8.I)
wire(n7.valid_down, n8.valid_up)
wire(n8.O, cls.O)
wire(n8.valid_down, cls.valid_down)
return _Module_0
Main = Module_0
fault_helpers.compile(
Main(),
"v./home/durst/dev/embeddedHaskellAetherling//test/no_bench/magma_examples/down_over_nested_to_down_over_flattened/down_over_nested_to_down_over_flattened_1 % 1thr.py"
)
n12 = DefineMap_T(2, 0, DefineMap_S(2, DefineAbs_Atom(True),
True))()
wire(n7.O, n12.I)
wire(n7.valid_down, n12.valid_up)
n13 = DefineFIFO(ST_TSeq(2, 0, ST_SSeq(2, ST_Int(8, True))),
1,
has_valid=True)()
wire(n12.O, n13.I)
wire(n12.valid_down, n13.valid_up)
n14 = DefineFIFO(ST_TSeq(2, 0, ST_SSeq(2, ST_Int(8, True))),
1,
has_valid=True)()
wire(n13.O, n14.I)
wire(n13.valid_down, n14.valid_up)
n15 = DefineFIFO(ST_TSeq(2, 0, ST_SSeq(2, ST_Int(8, True))),
1,
has_valid=True)()
wire(n14.O, n15.I)
wire(n14.valid_down, n15.valid_up)
wire(n15.O, cls.O)
wire(n15.valid_down, cls.valid_down)
return _Module_0
Main = Module_0
fault_helpers.compile(
Main(),
"v./home/durst/dev/embeddedHaskellAetherling//test/no_bench/magma_examples/map_to_unpartition/map_to_unpartition_2 % 1thr.py"
)
n1 = DefineFIFO(ST_TSeq(4, 0, ST_Int(8, True)), 1,
has_valid=True)()
wire(cls.I, n1.I)
wire(cls.valid_up, n1.valid_up)
n4 = DefineMap_T(4, 0, DefineAbs_Atom(True))()
wire(n1.O, n4.I)
wire(n1.valid_down, n4.valid_up)
n5 = DefineFIFO(ST_TSeq(4, 0, ST_Int(8, True)), 1,
has_valid=True)()
wire(n4.O, n5.I)
wire(n4.valid_down, n5.valid_up)
n6 = DefineFIFO(ST_TSeq(4, 0, ST_Int(8, True)), 1,
has_valid=True)()
wire(n5.O, n6.I)
wire(n5.valid_down, n6.valid_up)
n7 = DefineFIFO(ST_TSeq(4, 0, ST_Int(8, True)), 1,
has_valid=True)()
wire(n6.O, n7.I)
wire(n6.valid_down, n7.valid_up)
wire(n7.O, cls.O)
wire(n7.valid_down, cls.valid_down)
return _Module_0
Main = Module_0
fault_helpers.compile(
Main(),
"v./home/durst/dev/embeddedHaskellAetherling//test/no_bench/magma_examples/single_map_underutil/single_map_underutil_1 % 1thr.py"
)
wire(cls.valid_up, n1.valid_up)
n9 = DefineMap_T(4, 12, Module_0())()
wire(n1.O, n9.I)
wire(n1.valid_down, n9.valid_up)
n10 = DefineFIFO(ST_TSeq(4, 12, ST_SSeq(4, ST_Int(8, False))),
1,
has_valid=True)()
wire(n9.O, n10.I)
wire(n9.valid_down, n10.valid_up)
n11 = DefineFIFO(ST_TSeq(4, 12, ST_SSeq(4, ST_Int(8, False))),
1,
has_valid=True)()
wire(n10.O, n11.I)
wire(n10.valid_down, n11.valid_up)
n12 = DefineFIFO(ST_TSeq(4, 12, ST_SSeq(4, ST_Int(8, False))),
1,
has_valid=True)()
wire(n11.O, n12.I)
wire(n11.valid_down, n12.valid_up)
wire(n12.O, cls.O)
wire(n12.valid_down, cls.valid_down)
return _Module_1
Main = Module_1
fault_helpers.compile(
Main(),
"v./home/durst/dev/embeddedHaskellAetherling//test/no_bench/magma_examples/seq_and_stuple/seq_and_stuple_1 % 1thr.py"
)
wire(n12.valid_down, n28.valid_up)
n29 = DefineFIFO(ST_TSeq(2, 1,
ST_SSeq(4, ST_SSeq(3, ST_Int(8, False)))),
1,
has_valid=True)()
wire(n28.O, n29.I)
wire(n28.valid_down, n29.valid_up)
n30 = DefineFIFO(ST_TSeq(2, 1,
ST_SSeq(4, ST_SSeq(3, ST_Int(8, False)))),
1,
has_valid=True)()
wire(n29.O, n30.I)
wire(n29.valid_down, n30.valid_up)
n31 = DefineFIFO(ST_TSeq(2, 1,
ST_SSeq(4, ST_SSeq(3, ST_Int(8, False)))),
1,
has_valid=True)()
wire(n30.O, n31.I)
wire(n30.valid_down, n31.valid_up)
wire(n31.O, cls.O)
wire(n31.valid_down, cls.valid_down)
return _Module_0
Main = Module_0
fault_helpers.compile(
Main(),
"v./home/durst/dev/embeddedHaskellAetherling//test/no_bench/magma_examples/striple_to_seq/striple_to_seq_8 % 1thr.py"
)
wire(cls.valid_up, n1.valid_up)
n26 = DefineMap_T(2, 0, Module_0())()
wire(n1.O, n26.I)
wire(n1.valid_down, n26.valid_up)
n27 = DefineFIFO(ST_TSeq(2, 0, ST_TSeq(1, 1, ST_Int(16, False))),
1,
has_valid=True)()
wire(n26.O, n27.I)
wire(n26.valid_down, n27.valid_up)
n28 = DefineFIFO(ST_TSeq(2, 0, ST_TSeq(1, 1, ST_Int(16, False))),
1,
has_valid=True)()
wire(n27.O, n28.I)
wire(n27.valid_down, n28.valid_up)
n29 = DefineFIFO(ST_TSeq(2, 0, ST_TSeq(1, 1, ST_Int(16, False))),
1,
has_valid=True)()
wire(n28.O, n29.I)
wire(n28.valid_down, n29.valid_up)
wire(n29.O, cls.O)
wire(n29.valid_down, cls.valid_down)
return _Module_1
Main = Module_1
fault_helpers.compile(
Main(),
"v./home/durst/dev/embeddedHaskellAetherling//test/no_bench/magma_examples/tuple_reduce/tuple_reduce_1 % 2thr.py"
)
n9 = DefineMap_T(4, 4,
DefineUp_S(4, ST_Int(8, True), has_valid=True))()
wire(n6.O, n9.I)
wire(n6.valid_down, n9.valid_up)
n10 = DefineFIFO(ST_TSeq(4, 4, ST_SSeq(4, ST_Int(8, True))),
1,
has_valid=True)()
wire(n9.O, n10.I)
wire(n9.valid_down, n10.valid_up)
n11 = DefineFIFO(ST_TSeq(4, 4, ST_SSeq(4, ST_Int(8, True))),
1,
has_valid=True)()
wire(n10.O, n11.I)
wire(n10.valid_down, n11.valid_up)
n12 = DefineFIFO(ST_TSeq(4, 4, ST_SSeq(4, ST_Int(8, True))),
1,
has_valid=True)()
wire(n11.O, n12.I)
wire(n11.valid_down, n12.valid_up)
wire(n12.O, cls.O)
wire(n12.valid_down, cls.valid_down)
return _Module_0
Main = Module_0
fault_helpers.compile(
Main(),
"v./home/durst/dev/embeddedHaskellAetherling//test/no_bench/magma_examples/nested_map_to_nested_up/nested_map_to_nested_up_2 % 1thr.py"
)
