def test_2dlb_flicker_ce_with_no_stride():
scope = Scope()
c = coreir.Context()
cirb = CoreIRBackend(c)
testcircuit = DefineTwoDimensionalLineBuffer(cirb, Array[8, In(Bit)], 1, 1,
2, 2, 8, 8, 1, 1, 0, 0, True)
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=c,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for i in range(100000):
if i % 2 == 0:
sim.set_value(testcircuit.I[0][0], int2seq(1, 8), scope)
sim.set_value(testcircuit.CE, 1, scope)
else:
sim.set_value(testcircuit.I[0][0], int2seq(2, 8), scope)
sim.set_value(testcircuit.CE, 0, scope)
sim.evaluate()
sim.advance_cycle()
sim.evaluate()
print([
seq2int(sim.get_value(testcircuit.O[0][r][c], scope))
for r in range(2) for c in range(2)
])
print(sim.get_value(testcircuit.valid, scope))
# for some reason, lb going to 0 when flickering valid on and off for ce
for r in range(2):
for c in range(2):
assert (sim.get_value(testcircuit.valid, scope) == 0
or seq2int(sim.get_value(testcircuit.O[0][r][c],
scope)) != 0)
'O14',
Array[8, Out(Bit)],
'O15',
Array[8, Out(Bit)],
'valid_data_in',
In(Bit),
'ready_data_in',
Out(Bit),
'valid_data_out',
Out(Bit),
'ready_data_out',
In(Bit),
] + ClockInterface(has_ce=True)
partialParallel16Convolution = DefineCircuit(
'partialParallel16Convolution_Circuit', *args)
magmaInstance0 = DefineTwoDimensionalLineBuffer(Array[8, In(Bit)], 8, 2, 2, 2,
8, 8, 1, 1, 0, 0)()
magmaInstance1 = DefineCoreirConst(8, 1)()
magmaInstance2 = DefineCoreirConst(8, 1)()
magmaInstance3 = DefineCoreirConst(8, 1)()
magmaInstance4 = DefineCoreirConst(8, 1)()
magmaInstance5 = DefineCoreirConst(8, 1)()
magmaInstance6 = DefineCoreirConst(8, 1)()
magmaInstance7 = DefineCoreirConst(8, 1)()
magmaInstance8 = DefineCoreirConst(8, 1)()
magmaInstance9 = DefineCoreirConst(8, 1)()
magmaInstance10 = DefineCoreirConst(8, 1)()
magmaInstance11 = DefineCoreirConst(8, 1)()
magmaInstance12 = DefineCoreirConst(8, 1)()
magmaInstance13 = DefineCoreirConst(8, 1)()
magmaInstance14 = DefineCoreirConst(8, 1)()
magmaInstance15 = DefineCoreirConst(8, 1)()
def impl_test_2D_line_buffer(parameters: LineBufferParameters):
"""Instantiate a simulated line buffer with the specified parameters
and run it on test data sets."""
print(parameters.as_kwargs())
scope = Scope()
LineBufferDef = DefineTwoDimensionalLineBuffer(**parameters.as_kwargs())
window_count, parallelism, valid_count = parameters.internal_parameters()
window_x = parameters.window_x
window_y = parameters.window_y
sim = None
# We have to treat int (as bit array) and bit line buffers
# differently. Deal with these differences here (different random
# data generator, need int2seq/seq2int for ints). Ugly but better
# than 2 copies of this function.
token = parameters.magma_type
if token == Bit:
generators = make_bit_generators()
def set_value(bits):
sim.set_value(LineBufferDef.I, bits, scope)
def get_pixel(window_index, y, x):
return sim.get_value(LineBufferDef.O[window_index][y][x], scope)
else:
try:
bit_width = token.N
if token.T != Bit:
raise TypeError("Not a bit.")
except Exception as e:
raise TypeError("Type must be Bit or Array[n, Bit]") from e
generators = make_int_generators(bit_width)
def set_value(ints):
f = lambda px: int2seq(px, bit_width)
bit_arrays = [[f(px) for px in row] for row in ints]
sim.set_value(LineBufferDef.I, bit_arrays, scope)
def get_pixel(window_index, y, x):
return seq2int(
sim.get_value(LineBufferDef.O[window_index][y][x], scope))
for test_set in generate_test_sets_2D(generators, parameters):
sim = CoreIRSimulator(LineBufferDef,
LineBufferDef.CLK,
namespaces=[
"aetherlinglib", "commonlib", "mantle",
"coreir", "global"
])
sim.set_value(LineBufferDef.CE, 1, scope)
# List for recording sequence of valid outputs (in 4D format
# in header, skipping entries on cycles where valid is not
# asserted), and a helper function:
# tick_sim_collect_outputs ticks the simulation, appending any
# output received when the simulated module asserts valid.
actual = []
expected = expected_valid_outputs_2D(test_set, parameters)
quijibo = -1
def tick_sim_collect_outputs():
nonlocal quijibo
sim.evaluate()
quijibo += 1
# test1_scope = Scope(instance=LineBufferDef._instances[0], parent=scope)
# test2_scope = Scope(instance=LineBufferDef._instances[0]._instances[0], parent=scope)
# #print("testing test2 {}".format(sim.get_value(LineBufferDef._instances[0]._instances[0].O, test2_scope)))
# test3_scope = Scope(instance=LineBufferDef._instances[0]._instances[0]._instances[0], parent=test2_scope)
# test4_scope = Scope(instance=LineBufferDef._instances[0]._instances[0]._instances[0]._instances[0], parent=test3_scope)
# test5_scope = Scope(instance=LineBufferDef._instances[0]._instances[0]._instances[0]._instances[0]._instances[0],
# parent=test4_scope)
# test6_scope = Scope(
# instance=LineBufferDef._instances[0]._instances[0]._instances[0]._instances[0]._instances[1],
# parent=test4_scope)
# first_rb = LineBufferDef._instances[0]._instances[0]._instances[0]._instances[0]._instances[0]._instances[1]
# delayed_buffer_of_first_shift_register = Scope(
# instance=first_rb,
# parent=test5_scope
# )
# first_sipo = LineBufferDef._instances[0]._instances[0]._instances[0]._instances[0]._instances[0]._instances[0]
# sipo_of_first_shift_register = Scope(
# instance=first_sipo,
# parent=test5_scope
# )
# second_rb = LineBufferDef._instances[0]._instances[0]._instances[0]._instances[0]._instances[1]._instances[1]
# delayed_buffer_of_second_shift_register = Scope(
# instance=second_rb,
# parent=test5_scope
# )
# second_sipo = LineBufferDef._instances[0]._instances[0]._instances[0]._instances[0]._instances[1]._instances[0]
# sipo_of_second_shift_register = Scope(
# instance=second_sipo,
# parent=test5_scope
# )
# print("step {}: {}".format(quijibo, sim.get_value(LineBufferDef.valid, scope)))
# print("input {}: {}".format(quijibo, sim.get_value(LineBufferDef.I, scope)))
# print("lb output {}: {}".format(quijibo, sim.get_value(LineBufferDef._instances[0].O, scope)))
# print("lb valid {}: {}".format(quijibo, sim.get_value(LineBufferDef._instances[0].valid, scope)))
# print("first sipo input {}: {}".format(quijibo, sim.get_value(first_sipo.I, sipo_of_first_shift_register)))
# print("first sipo output {}: {}".format(quijibo, sim.get_value(first_sipo.defn._instances[0].O[2], sipo_of_first_shift_register)))
# print("first rb input {}: {}".format(quijibo, sim.get_value(first_sipo.defn._instances[1].I[0], delayed_buffer_of_first_shift_register)))
# print("first rb CE {}: {}".format(quijibo, sim.get_value(first_sipo.defn._instances[1].CE, delayed_buffer_of_first_shift_register)))
# print("first rb WE {}: {}".format(quijibo, sim.get_value(first_sipo.defn._instances[1].WE, delayed_buffer_of_first_shift_register)))
# print("first rb output {}: {}".format(quijibo, sim.get_value(first_rb.O, delayed_buffer_of_first_shift_register)))
# print("second sipo input {}: {}".format(quijibo, sim.get_value(second_sipo.I, sipo_of_second_shift_register)))
# print("second sipo output {}: {}".format(quijibo, sim.get_value(second_sipo.defn._instances[0].O[2], sipo_of_second_shift_register)))
# print("second rb input {}: {}".format(quijibo, sim.get_value(second_sipo.defn._instances[1].I[0], delayed_buffer_of_second_shift_register)))
# print("second rb CE {}: {}".format(quijibo, sim.get_value(second_sipo.defn._instances[1].CE, delayed_buffer_of_second_shift_register)))
# print("second rb WE {}: {}".format(quijibo, sim.get_value(second_sipo.defn._instances[1].WE, delayed_buffer_of_second_shift_register)))
# print("first rb output {}: {}".format(quijibo, sim.get_value(first_rb.O, delayed_buffer_of_first_shift_register)))
# # if len(LineBufferDef._instances) > 1:
# # print("db input {}: {}".format(quijibo, sim.get_value(LineBufferDef._instances[1].I, scope)))
# # print("db output {}: {}".format(quijibo, sim.get_value(LineBufferDef._instances[1].O, scope)))
# print("output {}: {}".format(quijibo, sim.get_value(LineBufferDef.O, scope)))
# print("\n")
if sim.get_value(LineBufferDef.valid, scope):
actual.append([ # Parallel output windows
[ # Rows
[ # Columns
get_pixel(window_index, y, x)
for x in range(window_x)
] for y in range(window_y)
] for window_index in range(parallelism)
])
sim.advance_cycle()
sim.evaluate()
for input_window in test_set:
set_value(input_window)
tick_sim_collect_outputs()
# Wait for a little extra after the last input because the
# line buffer may need a bit of extra time to emit the last
# windows.
extra_cycles = 16 + parameters.image_x * window_y + window_x
for i in range(extra_cycles):
if len(actual) >= len(expected): break
tick_sim_collect_outputs()
len_actual, len_expected = len(actual), len(expected)
actual_parallelism = len(LineBufferDef.O)
assert actual_parallelism == parallelism, \
f"Expected {parallelism} outputs per (valid) cycle, seem to " \
f"actually have {actual_parallelism}."
assert len_actual >= len_expected, \
f"Got {len_actual} outputs (counts of valid asserts); expected " \
f"{len_expected} outputs.\n" \
f"Waited {extra_cycles} cycles after last input."
print(parameters.as_kwargs())
fill_garbage_with_none(actual, expected)
print('\x1b[31mActual: ', actual, '\n\x1b[34mExpected: ', expected,
'\x1b[0m')
assert actual == expected, "Outputs don't match expected values."
'I15',
Array[8, In(Bit)],
'O0',
Array[8, Out(Bit)],
'valid_data_in',
In(Bit),
'ready_data_in',
Out(Bit),
'valid_data_out',
Out(Bit),
'ready_data_out',
In(Bit),
] + ClockInterface(has_ce=True)
downsample_256x256_to_32x32_16px_in_per_clk = DefineCircuit(
'downsample_256x256_to_32x32_16px_in_per_clk_Circuit', *args)
magmaInstance0 = DefineTwoDimensionalLineBuffer(Array[8, In(Bit)], 16, 1, 2, 2,
256, 256, 2, 2, 0, 0)()
magmaInstance1 = DefineNoop(
DefineTwoDimensionalLineBuffer(Array[8, In(Bit)], 16, 1, 2, 2, 256, 256, 2,
2, 0, 0))()
magmaInstance2 = DefineCoreirConst(8, 1)()
magmaInstance3 = DefineCoreirConst(8, 1)()
magmaInstance4 = DefineCoreirConst(8, 1)()
magmaInstance5 = DefineCoreirConst(8, 1)()
magmaInstance6 = DefineCoreirConst(8, 2)()
magmaInstance7 = DefineCoreirConst(8, 2)()
magmaInstance8 = DefineCoreirConst(8, 2)()
magmaInstance9 = DefineCoreirConst(8, 2)()
magmaInstance13 = DefineCoreirConst(8, 3)()
magmaInstance14 = DefineCoreirConst(8, 3)()
magmaInstance15 = DefineCoreirConst(8, 3)()
magmaInstance16 = DefineCoreirConst(8, 3)()
from mantle.coreir.arith import *
from mantle.coreir.logic import *
from mantle.coreir.compare import *
from mantle.coreir import DefineCoreirConst
from mantle.coreir.LUT import *
from aetherling.modules.upsample import *
from aetherling.modules.downsample import *
from aetherling.modules.reduce import *
from aetherling.modules.native_linebuffer.two_dimensional_native_linebuffer import DefineTwoDimensionalLineBuffer
c = coreir.Context()
cirb = CoreIRBackend(c)
args = ['I0', Array[8, In(Bit)], 'I1', Array[8, In(Bit)], 'O0', Array[8, Out(Bit)], 'valid_data_in', In(Bit), 'ready_data_in', Out(Bit), 'valid_data_out', Out(Bit), 'ready_data_out', In(Bit), ] + ClockInterface(has_ce=True)
downsampleStencilChain1Per32 = DefineCircuit('downsampleStencilChain1Per32_Circuit', *args)
magmaInstance0 = DefineTwoDimensionalLineBuffer(Array[8, In(Bit)], 2, 1, 2, 2, 16, 16, 2, 2, 0, 0)()
magmaInstance1 = DefineNoop(DefineTwoDimensionalLineBuffer(Array[8, In(Bit)], 2, 1, 2, 2, 16, 16, 2, 2, 0, 0))()
magmaInstance2 = DefineCoreirConst(8, 1)()
magmaInstance3 = DefineCoreirConst(8, 2)()
magmaInstance4 = DefineCoreirConst(8, 3)()
magmaInstance5 = DefineCoreirConst(8, 4)()
wire(magmaInstance0.O[0][0][0], magmaInstance1.in_O[0][0][0])
wire(magmaInstance0.O[0][0][1], magmaInstance1.in_O[0][0][1])
wire(magmaInstance0.O[0][1][0], magmaInstance1.in_O[0][1][0])
wire(magmaInstance0.O[0][1][1], magmaInstance1.in_O[0][1][1])
magmaInstance6 = DefineCoreirMul(8)()
magmaInstance7 = DefineCoreirMul(8)()
magmaInstance8 = DefineCoreirMul(8)()
magmaInstance9 = DefineCoreirMul(8)()
wire(magmaInstance1.O[0][0][0], magmaInstance6.I0)
wire(magmaInstance2.O, magmaInstance6.I1)
def test_2dlb_flicker_ce_with_2x2_stride_ross_clock_instructions():
scope = Scope()
c = coreir.Context()
cirb = CoreIRBackend(c)
testcircuit = DefineTwoDimensionalLineBuffer(cirb, Array[8, In(Bit)], 1, 1,
2, 2, 8, 8, 2, 2, 0, 0, True)
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=c,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
sim.set_value(testcircuit.CE, 1, scope)
sim.set_value(testcircuit.I[0][0], int2seq(1, 8), scope)
sim.evaluate()
sim.set_value(testcircuit.CLK, 1, scope)
sim.evaluate()
for i in range(100000):
sim.set_value(testcircuit.CLK, 0, scope)
sim.evaluate()
print("CLK: " + str(sim.get_value(testcircuit.CLK, scope)))
print("i" + str(i))
print("undelayed out: " + str([
seq2int(sim.get_value(testcircuit.undelayedO[0][r][c], scope))
for r in range(2) for c in range(2)
]))
print("out: " + str([
seq2int(sim.get_value(testcircuit.O[0][r][c], scope))
for r in range(2) for c in range(2)
]))
print("valid: " + str(sim.get_value(testcircuit.valid, scope)))
print("db CE: " + str(sim.get_value(testcircuit.dbCE, scope)))
print("db WE: " + str(sim.get_value(testcircuit.dbWE, scope)))
print("db RDATA: " + str([
seq2int(sim.get_value(testcircuit.RDATA, scope)[0][r][c])
for r in range(2) for c in range(2)
]))
print("db WDATA: " + str([
seq2int(sim.get_value(testcircuit.WDATA, scope)[0][r][c])
for r in range(2) for c in range(2)
]))
print("db RADDR: " +
str(seq2int(sim.get_value(testcircuit.RADDR, scope)[0])))
print("db WADDR: " +
str(seq2int(sim.get_value(testcircuit.WADDR, scope)[0])))
print("db RAM WE: " + str(sim.get_value(testcircuit.RAMWE, scope)))
print("")
print("")
sim.set_value(testcircuit.CLK, 1, scope)
sim.evaluate()
print("CLK: " + str(sim.get_value(testcircuit.CLK, scope)))
if i % 2 == 1:
sim.set_value(testcircuit.I[0][0], int2seq(1, 8), scope)
sim.set_value(testcircuit.CE, 1, scope)
else:
sim.set_value(testcircuit.I[0][0], int2seq(2, 8), scope)
sim.set_value(testcircuit.CE, 0, scope)
sim.evaluate()
def test_clock_adjusted_2dlb_flicker_ce_with_2x2_stride():
c = coreir.Context()
cirb = CoreIRBackend(c)
testcircuit = DefineTwoDimensionalLineBuffer(cirb, Array[8, In(Bit)], 1, 1,
2, 2, 8, 8, 2, 2, 0, 0, True)
magma.compile("vBuild/" + testcircuit.name,
testcircuit,
output="coreir-verilog",
passes=[
"rungenerators", "wireclocks-coreir",
"verifyconnectivity --noclkrst", "flattentypes",
"flatten", "verifyconnectivity --noclkrst",
"deletedeadinstances"
],
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
],
context=c)
tester = fault.Tester(testcircuit, testcircuit.CLK)
for i in range(30):
if i % 2 == 0:
tester.poke(testcircuit.I[0][0], 1)
tester.poke(testcircuit.CE, 1)
else:
tester.poke(testcircuit.I[0][0], 2)
tester.poke(testcircuit.CE, 0)
tester.eval()
tester.step(2)
tester.eval()
print_start_clock(tester)
print_nd_bit_array_port(tester, testcircuit.valid, name="valid")
print_nd_int_array_port(tester, testcircuit.O, name="O")
print_end_clock(tester)
#tester.print(testcircuit.O, f"{i}: %x \\n")
# tester.print(testcircuit.I, f"{start_string} {i} Input: %x\\n")
# for some reason, lb going to 0 when flickering valid on and off for ce
for r in range(2):
for c in range(2):
if r == 0 and c == 0:
inner_start_string = "[["
inner_end_string = ", "
elif c == 0:
inner_start_string = "["
inner_end_string = ", "
elif r == 1 and c == 1:
inner_start_string = ""
inner_end_string = "]], "
elif c == 1:
inner_start_string = ""
inner_end_string = "], "
#tester.print(testcircuit.O[0][r][c], f"{inner_start_string}%x{inner_end_string}")
#tester.expect(testcircuit.O[0][r][c], 1)
# tester.circuit.O[0][r][c].expect(1)
tester.compile_and_run(target="verilator",
skip_compile=True,
directory="vBuild/")
with open(get_fault_log(__file__, testcircuit.name)) as file:
results = eval("[" + file.read() + "]")
print(len(results))
print(results[0])
def test_2dlb_flicker_ce_with_2x2_stride():
scope = Scope()
c = coreir.Context()
cirb = CoreIRBackend(c)
testcircuit = DefineTwoDimensionalLineBuffer(cirb, Array[8, In(Bit)], 1, 1,
2, 2, 8, 8, 2, 2, 0, 0, True)
#magma.compile("2dlbflicker_1001pm_2_11_19_unflattened", testcircuit, output="coreir-verilog",
# passes=["rungenerators", "wireclocks-coreir", "verifyconnectivity --noclkrst", "verifyconnectivity --noclkrst", "deletedeadinstances"],
# namespaces=["aetherlinglib", "commonlib", "mantle", "coreir", "global"], context = c)
#magma.compile("2dlbflicker_912pm_2_11_19_flattened", testcircuit, output="coreir-verilog",
# passes=["rungenerators", "wireclocks-coreir", "verifyconnectivity --noclkrst", "flattentypes", "flatten", "verifyconnectivity --noclkrst", "deletedeadinstances"],
# namespaces=["aetherlinglib", "commonlib", "mantle", "coreir", "global"], context = c)
#tcm = GetCoreIRModule(cirb, testcircuit)
#cirb.context.run_passes(, )
#tcm.save_to_file("2dlbflicker.json")
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=c,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for i in range(100000):
if i % 2 == 0:
sim.set_value(testcircuit.I[0][0], int2seq(1, 8), scope)
sim.set_value(testcircuit.CE, 1, scope)
else:
sim.set_value(testcircuit.I[0][0], int2seq(2, 8), scope)
sim.set_value(testcircuit.CE, 0, scope)
sim.evaluate()
sim.advance_cycle()
sim.evaluate()
print("i" + str(i))
print("undelayed out: " + str([
seq2int(sim.get_value(testcircuit.undelayedO[0][r][c], scope))
for r in range(2) for c in range(2)
]))
print("out: " + str([
seq2int(sim.get_value(testcircuit.O[0][r][c], scope))
for r in range(2) for c in range(2)
]))
print("valid: " + str(sim.get_value(testcircuit.valid, scope)))
print("db CE: " + str(sim.get_value(testcircuit.dbCE, scope)))
print("db WE: " + str(sim.get_value(testcircuit.dbWE, scope)))
print("db RDATA: " + str([
seq2int(sim.get_value(testcircuit.RDATA, scope)[0][r][c])
for r in range(2) for c in range(2)
]))
print("db WDATA: " + str([
seq2int(sim.get_value(testcircuit.WDATA, scope)[0][r][c])
for r in range(2) for c in range(2)
]))
print("db RADDR: " +
str(seq2int(sim.get_value(testcircuit.RADDR, scope)[0])))
print("db WADDR: " +
str(seq2int(sim.get_value(testcircuit.WADDR, scope)[0])))
print("db RAM WE: " + str(sim.get_value(testcircuit.RAMWE, scope)))
print("")
print("")
'I31',
Array[8, In(Bit)],
'O0',
Array[8, Out(Bit)],
'valid_data_in',
In(Bit),
'ready_data_in',
Out(Bit),
'valid_data_out',
Out(Bit),
'ready_data_out',
In(Bit),
] + ClockInterface(has_ce=True)
downsample_256x256_to_32x32_32px_in_per_clk = DefineCircuit(
'downsample_256x256_to_32x32_32px_in_per_clk_Circuit', *args)
magmaInstance0 = DefineTwoDimensionalLineBuffer(Array[8, In(Bit)], 32, 1, 2, 2,
256, 256, 2, 2, 0, 0)()
magmaInstance1 = DefineNoop(
DefineTwoDimensionalLineBuffer(Array[8, In(Bit)], 32, 1, 2, 2, 256, 256, 2,
2, 0, 0))()
magmaInstance2 = DefineCoreirConst(8, 1)()
magmaInstance3 = DefineCoreirConst(8, 1)()
magmaInstance4 = DefineCoreirConst(8, 1)()
magmaInstance5 = DefineCoreirConst(8, 1)()
magmaInstance6 = DefineCoreirConst(8, 1)()
magmaInstance7 = DefineCoreirConst(8, 1)()
magmaInstance8 = DefineCoreirConst(8, 1)()
magmaInstance9 = DefineCoreirConst(8, 1)()
magmaInstance10 = DefineCoreirConst(8, 2)()
magmaInstance11 = DefineCoreirConst(8, 2)()
magmaInstance12 = DefineCoreirConst(8, 2)()
magmaInstance13 = DefineCoreirConst(8, 2)()