def test_one():
c = Canvas()
m1 = c.addGen(
Wire(nm='m1',
layer='M1',
direction='v',
clg=UncoloredCenterLineGrid(width=400, pitch=720, repeat=2),
spg=EnclosureGrid(pitch=720, stoppoint=360)))
m2 = c.addGen(
Wire(nm='m2',
layer='M2',
direction='h',
clg=UncoloredCenterLineGrid(width=400, pitch=720, repeat=5),
spg=EnclosureGrid(pitch=720, stoppoint=360)))
v1 = c.addGen(Via(nm='v1', layer='via1', h_clg=m2.clg, v_clg=m1.clg))
for i in [0, 2, 4]:
c.addWire(m1, 'a', None, i, (0, 1), (4, -1))
for i in [1, 3, 5]:
c.addWire(m1, 'b', None, i, (0, 1), (4, -1))
c.addWireAndViaSet('a', None, m2, v1, 2, [0, 2, 4])
c.addWireAndViaSet('b', None, m2, v1, 1, [1, 3, 5])
print(c.terminals)
c.computeBbox()
fn = "__json_via_set"
data = {
'bbox': c.bbox.toList(),
'globalRoutes': [],
'globalRouteGrid': [],
'terminals': c.removeDuplicates()
}
with open(mydir / (fn + "_cand"), "wt") as fp:
fp.write(json.dumps(data, indent=2) + '\n')
with open(mydir / (fn + "_gold"), "rt") as fp:
data2 = json.load(fp)
assert data == data2
def setup():
p = Pdk()
p.pdk['M2'] = {
'Direction': 'H',
'Width': 60,
'Pitch': 100,
'MinL': 10,
'EndToEnd': 10
}
p.pdk['M3'] = {
'Direction': 'V',
'Width': 50,
'Pitch': 100,
'MinL': 10,
'EndToEnd': 10
}
#
# Adjacent via violation
# ***** *****
# ^ ^
# WidthX + SpaceX > Pitch(X)
#
# Both okay below
#
p.pdk['V2'] = {
'Stack': ['M2', 'M3'],
'WidthX': 50,
'WidthY': 60,
'SpaceX': 50,
'SpaceY': 40,
'VencA_L': 0,
'VencA_H': 0,
'VencP_L': 0,
'VencP_H': 0
}
c = Canvas(p)
m2 = c.addGen(
Wire(nm='m2',
layer='M2',
direction='h',
clg=UncoloredCenterLineGrid(width=p['M2']['Width'],
pitch=p['M2']['Pitch']),
spg=EnclosureGrid(pitch=p['M3']['Pitch'],
stoppoint=p['M3']['Pitch'] // 2)))
m3 = c.addGen(
Wire(nm='m3',
layer='M3',
direction='v',
clg=UncoloredCenterLineGrid(width=p['M3']['Width'],
pitch=p['M3']['Pitch']),
spg=EnclosureGrid(pitch=p['M2']['Pitch'],
stoppoint=p['M2']['Pitch'] // 2)))
v2 = c.addGen(Via(nm='v2', layer='V2', h_clg=m2.clg, v_clg=m3.clg))
n = 40
gridlines = list(range(n))
for i in gridlines:
c.addWire(m3, 'a', None, i, (0, 1), (n + 1, -1))
for j in gridlines:
c.addWireAndViaSet('a', None, m2, v2, j + 1, gridlines)
return c, n