def iterblocks(self,loc=None):
inblock = (lambda i: INSTRUCTION_TYPES[i.type]!='control_flow')
l = []
seq = self.sequence(loc)
for i in seq:
if inblock(i):
l.append(i)
else:
# add branching instruction inside block:
l.append(i)
# check if branch is delayed (e.g. sparc)
# if so, include next (delay slot) instruction
if i.misc['delayed']:
try:
l.append(next(seq))
except StopIteration:
logger.warning('no instruction in delay slot')
# create block instance:
b = code.block(l)
b.misc['cfi'] = i
l = []
# return block with additional platform-specific misc infos
b=self.prog.codehelper(block=b)
yield b
if len(l)>0:
b = code.block(l)
b=self.prog.codehelper(block=b)
yield b
def iterblocks(self, loc=None):
"""Iterator over basic blocks. The :attr:`instruction.type`
attribute is used to detect the end of a block (type_control_flow).
The returned :class:`block` object is enhanced with plateform-specific
informations (see :attr:`block.misc`).
Arguments:
loc (Optional[cst]): the address of the first block
(defaults to the program's entrypoint).
Yields:
linear sweeped blocks of instructions from given address,
until :meth:`sequence` stops.
"""
inblock = (lambda i: INSTRUCTION_TYPES[i.type] != 'control_flow')
l = []
seq = self.sequence(loc)
for i in seq:
if inblock(i):
l.append(i)
else:
# add branching instruction inside block:
l.append(i)
# check if branch is delayed (e.g. sparc)
# if so, include next (delay slot) instruction
if i.misc['delayed']:
try:
l.append(next(seq))
except StopIteration:
logger.warning(u'no instruction in delay slot')
# create block instance:
b = code.block(l)
b.misc['cfi'] = i
l = []
# return block with additional platform-specific misc infos
b = self.prog.codehelper(block=b)
SIG_BLCK.emit(args=b)
yield b
if len(l) > 0:
b = code.block(l)
b = self.prog.codehelper(block=b)
SIG_BLCK.emit(args=b)
yield b
def iterblocks(self, loc=None):
"""Iterator over basic blocks. The :attr:`instruction.type`
attribute is used to detect the end of a block (type_control_flow).
The returned :class:`block` object is enhanced with plateform-specific
informations (see :attr:`block.misc`).
Arguments:
loc (Optional[cst]): the address of the first block
(defaults to the program's entrypoint).
Yields:
linear sweeped blocks of instructions from given address,
until :meth:`sequence` stops.
"""
l = []
if not self.prog.cpu:
logger.error("no cpu has been assigned to prog.")
return
if isinstance(loc, int):
loc = self.prog.cpu.cst(loc, self.prog.cpu.PC().size)
seq = self.sequence(loc)
is_delay_slot = False
for i in seq:
# add branching instruction inside block:
l.append(i)
if i.misc.get("delayed", False):
is_delay_slot = True
elif i.type == type_control_flow or is_delay_slot:
# check if branch is delayed (e.g. sparc)
# create block instance:
b = code.block(l)
l = []
is_delay_slot = False
SIG_BLCK.emit(args=b)
yield b
if len(l) > 0:
if is_delay_slot:
logger.warning("no instruction in delay slot")
b = code.block(l)
SIG_BLCK.emit(args=b)
yield b
def build(self,cpu):
instr = [i.build(cpu) for i in self]
b = block(instr)
b.map = self.map.build()
b.misc.update(self.misc)
return b
def build(self, cpu):
instr = [i.build(cpu) for i in self.instr]
b = block(instr)
b.map = self.map.build()
b.misc.update(self.misc)
return b
def init_spool(self,loc):
return [(loc,cfg.node(code.block([])))]