class ArchBF(Arch): memory_endness = Endness.LE bits = 64 vex_arch = None name = "BF" instruction_alignment = 1 # Things I did not want to include but were necessary unfortunately :-( # self.cs_mode = capstone.CS_MODE_LITTLE_ENDIAN if endness == 'Iend_LE' else capstone.CS_MODE_BIG_ENDIAN # END # registers is a dictionary mapping register names, to a tuple of # register offset, and their width, in bytes register_list = [ Register(name="ip", size=8, vex_offset=0), Register(name="ptr", size=8, vex_offset=8), Register(name="inout", size=1, vex_offset=16), Register(name="ip_at_syscall", size=8, vex_offset=24), ] ip_offset = 0 def __init__(self, endness=Endness.LE): # forces little endian super().__init__(Endness.LE)
class ArchPcode_DATA_BE_64_default(ArchPcode): name = 'DATA:BE:64:default' pcode_arch = 'DATA:BE:64:default' description = 'Raw Data File (Little Endian)' bits = 64 ip_offset = 0x80000000 sp_offset = 0x0 bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('sp', 8, 0x0), Register('r0', 8, 0x8), Register('contextreg', 4, 0x100) ]
def test_register(): from archinfo.arch import Register register = Register( name = 'MIPS', size = 8, vex_offset = 10, vex_name = 'xyz', subregisters = ['a', 'b'], alias_names = ('r0'), general_purpose = True, floating_point = True, vector = True, argument = True, persistent = True, default_value = ('a', 'global'), linux_entry_value = 'argv', concretize_unique = True, concrete = True, artificial = True) assert register.name == 'MIPS' assert register.size == 8 assert register.vex_offset == 10 assert register.vex_name == "xyz" assert register.subregisters == ['a', 'b'] assert register.alias_names == ('r0') assert register.general_purpose assert register.floating_point assert register.vector assert register.argument assert register.persistent assert register.default_value == ('a', 'global') assert register.linux_entry_value == 'argv' assert register.concretize_unique assert register.concrete assert register.artificial
class ArchPcode_6805_BE_16_default(ArchPcode): name = '6805:BE:16:default' pcode_arch = '6805:BE:16:default' description = '6805 Microcontroller Family' bits = 16 ip_offset = 0x20 sp_offset = 0x22 bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('swi_vector', 2, 0x3ffc), Register('a', 1, 0x0), Register('x', 1, 0x1), Register('pc', 2, 0x20, alias_names=('ip', )), Register('sp', 2, 0x22), Register('h', 1, 0x30), Register('i', 1, 0x31), Register('n', 1, 0x32), Register('z', 1, 0x33), Register('c', 1, 0x34) ]
class ArchPcode_JVM_BE_32_default(ArchPcode): name = 'JVM:BE:32:default' pcode_arch = 'JVM:BE:32:default' description = 'Generic JVM' bits = 32 ip_offset = 0xc sp_offset = 0x8 bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('cat2_return_value', 8, 0x0), Register('return_value', 4, 0x4), Register('sp', 4, 0x8), Register('pc', 4, 0xc, alias_names=('ip',)), Register('switch_target', 4, 0x10), Register('return_address', 4, 0x14), Register('call_target', 4, 0x18), Register('lva', 4, 0x1c), Register('switch_ctrl', 16, 0x100) ]
class ArchPcode_M8C_BE_16_default(ArchPcode): name = 'M8C:BE:16:default' pcode_arch = 'M8C:BE:16:default' description = 'Cypress M8C Microcontroller Family' bits = 16 ip_offset = 0x10 sp_offset = 0x2 bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('a', 1, 0x0), Register('x', 1, 0x1), Register('sp', 1, 0x2), Register('f', 1, 0x3), Register('pc', 2, 0x10, alias_names=('ip',)), Register('contextreg', 4, 0x30) ]
class ArchPcode_Toy_LE_32_wordSize2(ArchPcode): name = 'Toy:LE:32:wordSize2' pcode_arch = 'Toy:LE:32:wordSize2' description = 'Toy (test) processor 32-bit little-endian (wordsize=2)' bits = 32 ip_offset = 0x103c sp_offset = 0x1034 bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('r0', 4, 0x1000), Register('r0l', 2, 0x1000), Register('r0h', 2, 0x1002), Register('r1', 4, 0x1004), Register('r1l', 2, 0x1004), Register('r1h', 2, 0x1006), Register('r2', 4, 0x1008), Register('r2l', 2, 0x1008), Register('r2h', 2, 0x100a), Register('r3', 4, 0x100c), Register('r3l', 2, 0x100c), Register('r3h', 2, 0x100e), Register('r4', 4, 0x1010), Register('r4l', 2, 0x1010), Register('r4h', 2, 0x1012), Register('r5', 4, 0x1014), Register('r5l', 2, 0x1014), Register('r5h', 2, 0x1016), Register('r6', 4, 0x1018), Register('r6l', 2, 0x1018), Register('r6h', 2, 0x101a), Register('r7', 4, 0x101c), Register('r7l', 2, 0x101c), Register('r7h', 2, 0x101e), Register('r8', 4, 0x1020), Register('r8l', 2, 0x1020), Register('r8h', 2, 0x1022), Register('r9', 4, 0x1024), Register('r9l', 2, 0x1024), Register('r9h', 2, 0x1026), Register('r10', 4, 0x1028), Register('r10l', 2, 0x1028), Register('r10h', 2, 0x102a), Register('r11', 4, 0x102c), Register('r11l', 2, 0x102c), Register('r11h', 2, 0x102e), Register('r12', 4, 0x1030), Register('r12l', 2, 0x1030), Register('r12h', 2, 0x1032), Register('sp', 4, 0x1034), Register('spl', 2, 0x1034), Register('sph', 2, 0x1036), Register('lr', 4, 0x1038), Register('lrl', 2, 0x1038), Register('lrh', 2, 0x103a), Register('pc', 4, 0x103c, alias_names=('ip', )), Register('pcl', 2, 0x103c), Register('pch', 2, 0x103e), Register('c', 1, 0x1100), Register('z', 1, 0x1101), Register('n', 1, 0x1102), Register('v', 1, 0x1103) ]
class ArchPcode_dsPIC33F_LE_24_default(ArchPcode): name = 'dsPIC33F:LE:24:default' pcode_arch = 'dsPIC33F:LE:24:default' description = 'dsPIC33F' bits = 24 ip_offset = 0x2e sp_offset = 0x1e bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('w1w0', 4, 0x0), Register('w0', 2, 0x0), Register('w0byte', 1, 0x0), Register('w1', 2, 0x2), Register('w1byte', 1, 0x2), Register('w3w2', 4, 0x4), Register('w2', 2, 0x4), Register('w2byte', 1, 0x4), Register('w3', 2, 0x6), Register('w3byte', 1, 0x6), Register('w5w4', 4, 0x8), Register('w4', 2, 0x8), Register('w4byte', 1, 0x8), Register('w5', 2, 0xa), Register('w5byte', 1, 0xa), Register('w7w6', 4, 0xc), Register('w6', 2, 0xc), Register('w6byte', 1, 0xc), Register('w7', 2, 0xe), Register('w7byte', 1, 0xe), Register('w9w8', 4, 0x10), Register('w8', 2, 0x10), Register('w8byte', 1, 0x10), Register('w9', 2, 0x12), Register('w9byte', 1, 0x12), Register('w11w10', 4, 0x14), Register('w10', 2, 0x14), Register('w10byte', 1, 0x14), Register('w11', 2, 0x16), Register('w11byte', 1, 0x16), Register('w13w12', 4, 0x18), Register('w12', 2, 0x18), Register('w12byte', 1, 0x18), Register('w13', 2, 0x1a), Register('w13byte', 1, 0x1a), Register('w15w14', 4, 0x1c), Register('w14', 2, 0x1c), Register('w14byte', 1, 0x1c), Register('w15', 2, 0x1e), Register('w15byte', 1, 0x1e), Register('splim', 2, 0x20), Register('acca', 6, 0x22), Register('accal', 2, 0x22), Register('accah', 2, 0x24), Register('accau', 2, 0x26), Register('accb', 6, 0x28), Register('accbl', 2, 0x28), Register('accbh', 2, 0x2a), Register('accbu', 2, 0x2c), Register('pc', 3, 0x2e, alias_names=('ip', )), Register('tblpag', 1, 0x31), Register('psvpag', 1, 0x33), Register('rcount', 2, 0x36), Register('dcount', 2, 0x38), Register('dostart', 3, 0x3a), Register('doend', 3, 0x3c), Register('corcon', 2, 0x44), Register('modcon', 2, 0x46), Register('xmodsrt', 2, 0x48), Register('xmodend', 2, 0x4a), Register('ymodsrt', 2, 0x4c), Register('ymodend', 2, 0x4e), Register('xbrev', 2, 0x50), Register('disicnt', 2, 0x52), Register('shadow_w0', 2, 0x0), Register('shadow_w1', 2, 0x2), Register('shadow_w2', 2, 0x4), Register('shadow_w3', 2, 0x6), Register('srl', 1, 0x400), Register('srh', 1, 0x401), Register('srh_oa', 1, 0x600), Register('srh_ob', 1, 0x601), Register('srh_sa', 1, 0x602), Register('srh_sb', 1, 0x603), Register('srh_oab', 1, 0x604), Register('srh_sab', 1, 0x605), Register('srh_da', 1, 0x606), Register('srh_dc', 1, 0x607), Register('srl_ipl2', 1, 0x608), Register('srl_ipl1', 1, 0x609), Register('srl_ipl0', 1, 0x60a), Register('srl_ra', 1, 0x60b), Register('srl_n', 1, 0x60c), Register('srl_ov', 1, 0x60d), Register('srl_z', 1, 0x60e), Register('srl_c', 1, 0x60f), Register('disi', 1, 0x610), Register('shadow_srh_dc', 1, 0x611), Register('shadow_srl_n', 1, 0x612), Register('shadow_srl_ov', 1, 0x613), Register('shadow_srl_z', 1, 0x614), Register('shadow_srl_c', 1, 0x615), Register('dostart_shadow', 3, 0x800), Register('doend_shadow', 3, 0x803), Register('wdtcount', 2, 0xa00), Register('wdtprescalara', 2, 0xa02), Register('wdtprescalarb', 2, 0xa04), Register('corcon_var', 1, 0xc00), Register('corcon_ipl3', 1, 0xc01), Register('corcon_psv', 1, 0xc02), Register('corcon_sfa', 1, 0xc03), Register('dcount_shadow', 2, 0x1000), Register('skipnextflag', 1, 0x1200), Register('contextreg', 4, 0x1400) ]
class ArchPcode_PIC_12_LE_16_PIC_12C5xx(ArchPcode): name = 'PIC-12:LE:16:PIC-12C5xx' pcode_arch = 'PIC-12:LE:16:PIC-12C5xx' description = 'PIC-12C5xx' bits = 16 ip_offset = 0x0 sp_offset = 0x2 bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('indf', 1, 0x0), Register('tmr0', 1, 0x1), Register('pcl.0', 1, 0x2), Register('status.0', 1, 0x3), Register('fsr.0', 1, 0x4), Register('osccal', 1, 0x5), Register('gpio', 1, 0x6), Register('pc', 2, 0x0, alias_names=('ip', )), Register('stkptr', 1, 0x2), Register('w', 1, 0x3), Register('pcl', 1, 0x4), Register('fsr', 1, 0x5), Register('status', 1, 0x6), Register('pa', 1, 0x7), Register('z', 1, 0x8), Register('dc', 1, 0x9), Register('c', 1, 0xa), Register('option', 1, 0xb), Register('tris', 1, 0x20) ]
class ArchPcode_ARM_LE_32_v4t(ArchPcode): name = 'ARM:LE:32:v4t' pcode_arch = 'ARM:LE:32:v4t' description = 'Generic ARM/Thumb v4 little endian (T-variant)' bits = 32 ip_offset = 0x5c sp_offset = 0x54 bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('contextreg', 8, 0x0), Register('r0', 4, 0x20), Register('r1', 4, 0x24), Register('r2', 4, 0x28), Register('r3', 4, 0x2c), Register('r4', 4, 0x30), Register('r5', 4, 0x34), Register('r6', 4, 0x38), Register('r7', 4, 0x3c), Register('r8', 4, 0x40), Register('r9', 4, 0x44), Register('r10', 4, 0x48), Register('r11', 4, 0x4c), Register('r12', 4, 0x50), Register('sp', 4, 0x54), Register('lr', 4, 0x58), Register('pc', 4, 0x5c, alias_names=('ip', )), Register('ng', 1, 0x60), Register('zr', 1, 0x61), Register('cy', 1, 0x62), Register('ov', 1, 0x63), Register('tmpng', 1, 0x64), Register('tmpzr', 1, 0x65), Register('tmpcy', 1, 0x66), Register('tmpov', 1, 0x67), Register('shift_carry', 1, 0x68), Register('tb', 1, 0x69), Register('q', 1, 0x6a), Register('ge1', 1, 0x6b), Register('ge2', 1, 0x6c), Register('ge3', 1, 0x6d), Register('ge4', 1, 0x6e), Register('cpsr', 4, 0x70), Register('spsr', 4, 0x74), Register('mult_addr', 4, 0x80), Register('r14_svc', 4, 0x84), Register('r13_svc', 4, 0x88), Register('spsr_svc', 4, 0x8c), Register('mult_dat16', 16, 0x90), Register('mult_dat8', 8, 0x90), Register('fpsr', 4, 0xa0), Register('isamodeswitch', 1, 0xb0), Register('fp0', 10, 0x100), Register('fp1', 10, 0x10a), Register('fp2', 10, 0x114), Register('fp3', 10, 0x11e), Register('fp4', 10, 0x128), Register('fp5', 10, 0x132), Register('fp6', 10, 0x13c), Register('fp7', 10, 0x146), Register('cr0', 4, 0x200), Register('cr1', 4, 0x204), Register('cr2', 4, 0x208), Register('cr3', 4, 0x20c), Register('cr4', 4, 0x210), Register('cr5', 4, 0x214), Register('cr6', 4, 0x218), Register('cr7', 4, 0x21c), Register('cr8', 4, 0x220), Register('cr9', 4, 0x224), Register('cr10', 4, 0x228), Register('cr11', 4, 0x22c), Register('cr12', 4, 0x230), Register('cr13', 4, 0x234), Register('cr14', 4, 0x238), Register('cr15', 4, 0x23c) ]
class ArchPcode_8051_BE_16_default(ArchPcode): name = '8051:BE:16:default' pcode_arch = '8051:BE:16:default' description = '8051 Microcontroller Family' bits = 16 ip_offset = 0x44 sp_offset = 0x40 bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('r0r1r2r3', 4, 0x0), Register('r0r1', 2, 0x0), Register('r0', 1, 0x0), Register('r1r2r3', 3, 0x1), Register('r2r1', 2, 0x1), Register('r1', 1, 0x1), Register('r2r3', 2, 0x2), Register('r2', 1, 0x2), Register('r3', 1, 0x3), Register('r4r5r6r7', 4, 0x4), Register('r4r5', 2, 0x4), Register('r4', 1, 0x4), Register('r5r6r7', 3, 0x5), Register('r5', 1, 0x5), Register('r6r7', 2, 0x6), Register('r6', 1, 0x6), Register('r7', 1, 0x7), Register('ab', 2, 0xa), Register('b', 1, 0xa), Register('acc', 1, 0xb), Register('sp', 1, 0x40), Register('pc', 2, 0x44, alias_names=('ip',)), Register('psw', 1, 0x48), Register('jumptableguard1', 1, 0x70), Register('jumptableguard2', 1, 0x71), Register('dptr', 2, 0x82), Register('dph', 1, 0x82), Register('dpl', 1, 0x83) ]
class ArchPcode_CP1600_BE_16_default(ArchPcode): name = 'CP1600:BE:16:default' pcode_arch = 'CP1600:BE:16:default' description = 'General Instruments CP1600' bits = 16 ip_offset = 0xe sp_offset = 0xc bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('r0', 2, 0x0), Register('r1', 2, 0x2), Register('r2', 2, 0x4), Register('r3', 2, 0x6), Register('r4', 2, 0x8), Register('r5', 2, 0xa), Register('r6', 2, 0xc), Register('r7', 2, 0xe, alias_names=('pc', 'ip')), Register('i', 1, 0x10), Register('c', 1, 0x11), Register('o', 1, 0x12), Register('z', 1, 0x13), Register('s', 1, 0x14), Register('contextreg', 4, 0x20) ]
class ArchPcode_68000_BE_32_default(ArchPcode): name = '68000:BE:32:default' pcode_arch = '68000:BE:32:default' description = 'Motorola 32-bit 68040' bits = 32 ip_offset = 0x50 sp_offset = 0x3c bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('d0', 4, 0x0), Register('d0w', 2, 0x2), Register('d0b', 1, 0x3), Register('d1', 4, 0x4), Register('d1w', 2, 0x6), Register('d1b', 1, 0x7), Register('d2', 4, 0x8), Register('d2w', 2, 0xa), Register('d2b', 1, 0xb), Register('d3', 4, 0xc), Register('d3w', 2, 0xe), Register('d3b', 1, 0xf), Register('d4', 4, 0x10), Register('d4w', 2, 0x12), Register('d4b', 1, 0x13), Register('d5', 4, 0x14), Register('d5w', 2, 0x16), Register('d5b', 1, 0x17), Register('d6', 4, 0x18), Register('d6w', 2, 0x1a), Register('d6b', 1, 0x1b), Register('d7', 4, 0x1c), Register('d7w', 2, 0x1e), Register('d7b', 1, 0x1f), Register('a0', 4, 0x20), Register('a0w', 2, 0x22), Register('a0b', 1, 0x23), Register('a1', 4, 0x24), Register('a1w', 2, 0x26), Register('a1b', 1, 0x27), Register('a2', 4, 0x28), Register('a2w', 2, 0x2a), Register('a2b', 1, 0x2b), Register('a3', 4, 0x2c), Register('a3w', 2, 0x2e), Register('a3b', 1, 0x2f), Register('a4', 4, 0x30), Register('a4w', 2, 0x32), Register('a4b', 1, 0x33), Register('a5', 4, 0x34), Register('a5w', 2, 0x36), Register('a5b', 1, 0x37), Register('a6', 4, 0x38), Register('a6w', 2, 0x3a), Register('a6b', 1, 0x3b), Register('sp', 4, 0x3c), Register('a7w', 2, 0x3e), Register('a7b', 1, 0x3f), Register('tf', 1, 0x40), Register('svf', 1, 0x41), Register('ipl', 1, 0x42), Register('xf', 1, 0x43), Register('nf', 1, 0x44), Register('zf', 1, 0x45), Register('vf', 1, 0x46), Register('cf', 1, 0x47), Register('pc', 4, 0x50, alias_names=('ip', )), Register('fpcr', 4, 0xb0), Register('fpsr', 4, 0xb4), Register('fpiar', 4, 0xb8), Register('crp', 8, 0xe0), Register('isp', 4, 0x100), Register('msp', 4, 0x104), Register('vbr', 4, 0x108), Register('cacr', 4, 0x10c), Register('caar', 4, 0x110), Register('ac0', 4, 0x114), Register('ac1', 4, 0x118), Register('usp', 4, 0x11c), Register('tt0', 4, 0x120), Register('tt1', 4, 0x124), Register('sfc', 4, 0x140), Register('dfc', 4, 0x144), Register('tc', 4, 0x148), Register('itt0', 4, 0x14c), Register('itt1', 4, 0x150), Register('dtt0', 4, 0x154), Register('dtt1', 4, 0x158), Register('mmusr', 4, 0x15c), Register('urp', 4, 0x160), Register('srp', 4, 0x164), Register('pcr', 4, 0x168), Register('cac', 4, 0x16c), Register('buscr', 4, 0x180), Register('mbb', 4, 0x184), Register('rambar0', 4, 0x188), Register('rambar1', 4, 0x18c), Register('sr', 2, 0x200), Register('acusr', 2, 0x202), Register('glbdenom', 4, 0x300), Register('movemptr', 4, 0x304), Register('contextreg', 4, 0x400), Register('fp0', 12, 0x700), Register('fp1', 12, 0x70c), Register('fp2', 12, 0x718), Register('fp3', 12, 0x724), Register('fp4', 12, 0x730), Register('fp5', 12, 0x73c), Register('fp6', 12, 0x748), Register('fp7', 12, 0x754) ]
class ArchPcode_HCS12_BE_24_default(ArchPcode): name = 'HCS12:BE:24:default' pcode_arch = 'HCS12:BE:24:default' description = 'HCS12X Microcontroller Family' bits = 24 ip_offset = 0x24 sp_offset = 0x2a bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('gpage', 1, 0x10), Register('direct', 1, 0x11), Register('rpage', 1, 0x16), Register('epage', 1, 0x17), Register('ppage', 1, 0x30), Register('d', 2, 0x0), Register('a', 1, 0x0), Register('b', 1, 0x1), Register('ix', 2, 0x10), Register('ixh', 1, 0x10), Register('ixl', 1, 0x11), Register('iy', 2, 0x12), Register('iyh', 1, 0x12), Register('iyl', 1, 0x13), Register('tmp2', 2, 0x14), Register('tmp2h', 1, 0x14), Register('tmp2l', 1, 0x15), Register('tmp3', 2, 0x16), Register('tmp3h', 1, 0x16), Register('tmp3l', 1, 0x17), Register('tmp1', 2, 0x18), Register('tmp1h', 1, 0x18), Register('tmp1l', 1, 0x19), Register('pce', 3, 0x23), Register('pc', 2, 0x24, alias_names=('ip', )), Register('pch', 1, 0x24), Register('pcl', 1, 0x25), Register('sp', 2, 0x2a), Register('sph', 1, 0x2a), Register('spl', 1, 0x2b), Register('ccrw', 2, 0x30), Register('ccrh', 1, 0x30), Register('ccr', 1, 0x31), Register('physpage', 3, 0x32), Register('contextreg', 4, 0x40), Register('r0', 2, 0x100), Register('r0.h', 1, 0x100), Register('r0.l', 1, 0x101), Register('r1', 2, 0x102), Register('r1.h', 1, 0x102), Register('r1.l', 1, 0x103), Register('r2', 2, 0x104), Register('r2.h', 1, 0x104), Register('r2.l', 1, 0x105), Register('r3', 2, 0x106), Register('r3.h', 1, 0x106), Register('r3.l', 1, 0x107), Register('r4', 2, 0x108), Register('r4.h', 1, 0x108), Register('r4.l', 1, 0x109), Register('r5', 2, 0x10a), Register('r5.h', 1, 0x10a), Register('r5.l', 1, 0x10b), Register('r6', 2, 0x10c), Register('r6.h', 1, 0x10c), Register('r6.l', 1, 0x10d), Register('r7', 2, 0x10e), Register('r7.h', 1, 0x10e), Register('r7.l', 1, 0x10f), Register('xpc', 2, 0x110), Register('xccr', 2, 0x112), Register('xc', 1, 0x120), Register('xv', 1, 0x121), Register('xz', 1, 0x122), Register('xn', 1, 0x123) ]
class ArchPcode_MIPS_LE_32_default(ArchPcode): name = 'MIPS:LE:32:default' pcode_arch = 'MIPS:LE:32:default' description = 'MIPS32 32-bit addresses, little endian, with mips16e' bits = 32 ip_offset = 0x80 sp_offset = 0x74 bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('zero', 4, 0x0), Register('at', 4, 0x4), Register('v0', 4, 0x8), Register('v1', 4, 0xc), Register('a0', 4, 0x10), Register('a1', 4, 0x14), Register('a2', 4, 0x18), Register('a3', 4, 0x1c), Register('t0', 4, 0x20), Register('t1', 4, 0x24), Register('t2', 4, 0x28), Register('t3', 4, 0x2c), Register('t4', 4, 0x30), Register('t5', 4, 0x34), Register('t6', 4, 0x38), Register('t7', 4, 0x3c), Register('s0', 4, 0x40), Register('s1', 4, 0x44), Register('s2', 4, 0x48), Register('s3', 4, 0x4c), Register('s4', 4, 0x50), Register('s5', 4, 0x54), Register('s6', 4, 0x58), Register('s7', 4, 0x5c), Register('t8', 4, 0x60), Register('t9', 4, 0x64), Register('k0', 4, 0x68), Register('k1', 4, 0x6c), Register('gp', 4, 0x70), Register('sp', 4, 0x74), Register('s8', 4, 0x78), Register('ra', 4, 0x7c), Register('pc', 4, 0x80, alias_names=('ip', )), Register('f0_1', 8, 0x1000), Register('f1', 4, 0x1000), Register('f0', 4, 0x1004), Register('f2_3', 8, 0x1008), Register('f3', 4, 0x1008), Register('f2', 4, 0x100c), Register('f4_5', 8, 0x1010), Register('f5', 4, 0x1010), Register('f4', 4, 0x1014), Register('f6_7', 8, 0x1018), Register('f7', 4, 0x1018), Register('f6', 4, 0x101c), Register('f8_9', 8, 0x1020), Register('f9', 4, 0x1020), Register('f8', 4, 0x1024), Register('f10_11', 8, 0x1028), Register('f11', 4, 0x1028), Register('f10', 4, 0x102c), Register('f12_13', 8, 0x1030), Register('f13', 4, 0x1030), Register('f12', 4, 0x1034), Register('f14_15', 8, 0x1038), Register('f15', 4, 0x1038), Register('f14', 4, 0x103c), Register('f16_17', 8, 0x1040), Register('f17', 4, 0x1040), Register('f16', 4, 0x1044), Register('f18_19', 8, 0x1048), Register('f19', 4, 0x1048), Register('f18', 4, 0x104c), Register('f20_21', 8, 0x1050), Register('f21', 4, 0x1050), Register('f20', 4, 0x1054), Register('f22_23', 8, 0x1058), Register('f23', 4, 0x1058), Register('f22', 4, 0x105c), Register('f24_25', 8, 0x1060), Register('f25', 4, 0x1060), Register('f24', 4, 0x1064), Register('f26_27', 8, 0x1068), Register('f27', 4, 0x1068), Register('f26', 4, 0x106c), Register('f28_29', 8, 0x1070), Register('f29', 4, 0x1070), Register('f28', 4, 0x1074), Register('f30_31', 8, 0x1078), Register('f31', 4, 0x1078), Register('f30', 4, 0x107c), Register('fir', 4, 0x1200), Register('fccr', 4, 0x1204), Register('fexr', 4, 0x1208), Register('fenr', 4, 0x120c), Register('fcsr', 4, 0x1210), Register('index', 4, 0x2000), Register('random', 4, 0x2004), Register('entrylo0', 4, 0x2008), Register('entrylo1', 4, 0x200c), Register('context', 4, 0x2010), Register('pagemask', 4, 0x2014), Register('wired', 4, 0x2018), Register('hwrena', 4, 0x201c), Register('badvaddr', 4, 0x2020), Register('count', 4, 0x2024), Register('entryhi', 4, 0x2028), Register('compare', 4, 0x202c), Register('status', 4, 0x2030), Register('cause', 4, 0x2034), Register('epc', 4, 0x2038), Register('prid', 4, 0x203c), Register('config', 4, 0x2040), Register('lladdr', 4, 0x2044), Register('watchlo', 4, 0x2048), Register('watchhi', 4, 0x204c), Register('xcontext', 4, 0x2050), Register('cop0_reg21', 4, 0x2054), Register('cop0_reg22', 4, 0x2058), Register('debug', 4, 0x205c), Register('depc', 4, 0x2060), Register('perfcnt', 4, 0x2064), Register('errctl', 4, 0x2068), Register('cacheerr', 4, 0x206c), Register('taglo', 4, 0x2070), Register('taghi', 4, 0x2074), Register('errorepc', 4, 0x2078), Register('desave', 4, 0x207c), Register('mvpcontrol', 4, 0x2100), Register('vpecontrol', 4, 0x2104), Register('tcstatus', 4, 0x2108), Register('cop0_reg3.1', 4, 0x210c), Register('contextconfig', 4, 0x2110), Register('pagegrain', 4, 0x2114), Register('srsconf0', 4, 0x2118), Register('cop0_reg7.1', 4, 0x211c), Register('cop0_reg8.1', 4, 0x2120), Register('cop0_reg9.1', 4, 0x2124), Register('cop0_reg10.1', 4, 0x2128), Register('cop0_reg11.1', 4, 0x212c), Register('intctl', 4, 0x2130), Register('cop0_reg13.1', 4, 0x2134), Register('cop0_reg14.1', 4, 0x2138), Register('ebase', 4, 0x213c), Register('config1', 4, 0x2140), Register('cop0_reg17.1', 4, 0x2144), Register('watchlo.1', 4, 0x2148), Register('watchhi.1', 4, 0x214c), Register('cop0_reg20.1', 4, 0x2150), Register('cop0_reg21.1', 4, 0x2154), Register('cop0_reg22.1', 4, 0x2158), Register('tracecontrol', 4, 0x215c), Register('cop0_reg24.1', 4, 0x2160), Register('perfcnt.1', 4, 0x2164), Register('cop0_reg26.1', 4, 0x2168), Register('cacheerr.1', 4, 0x216c), Register('datalo.1', 4, 0x2170), Register('datahi.1', 4, 0x2174), Register('cop0_reg30.1', 4, 0x2178), Register('cop0_reg31.1', 4, 0x217c), Register('mvpconf0', 4, 0x2200), Register('vpeconf0', 4, 0x2204), Register('tcbind', 4, 0x2208), Register('cop0_reg3.2', 4, 0x220c), Register('cop0_reg4.2', 4, 0x2210), Register('cop0_reg5.2', 4, 0x2214), Register('srsconf1', 4, 0x2218), Register('cop0_reg7.2', 4, 0x221c), Register('cop0_reg8.2', 4, 0x2220), Register('cop0_reg9.2', 4, 0x2224), Register('cop0_reg10.2', 4, 0x2228), Register('cop0_reg11.2', 4, 0x222c), Register('srsctl', 4, 0x2230), Register('cop0_reg13.2', 4, 0x2234), Register('cop0_reg14.2', 4, 0x2238), Register('cop0_reg15.2', 4, 0x223c), Register('config2', 4, 0x2240), Register('cop0_reg17.2', 4, 0x2244), Register('watchlo.2', 4, 0x2248), Register('watchhi.2', 4, 0x224c), Register('cop0_reg20.2', 4, 0x2250), Register('cop0_reg21.2', 4, 0x2254), Register('cop0_reg22.2', 4, 0x2258), Register('tracecontrol2', 4, 0x225c), Register('cop0_reg24.2', 4, 0x2260), Register('perfcnt.2', 4, 0x2264), Register('cop0_reg26.2', 4, 0x2268), Register('cacheerr.2', 4, 0x226c), Register('taglo.2', 4, 0x2270), Register('taghi.2', 4, 0x2274), Register('cop0_reg30.2', 4, 0x2278), Register('cop0_reg31.2', 4, 0x227c), Register('mvpconf1', 4, 0x2300), Register('vpeconf1', 4, 0x2304), Register('tcrestart', 4, 0x2308), Register('cop0_reg3.3', 4, 0x230c), Register('cop0_reg4.3', 4, 0x2310), Register('cop0_reg5.3', 4, 0x2314), Register('srsconf2', 4, 0x2318), Register('cop0_reg7.3', 4, 0x231c), Register('cop0_reg8.3', 4, 0x2320), Register('cop0_reg9.3', 4, 0x2324), Register('cop0_reg10.3', 4, 0x2328), Register('cop0_reg11.3', 4, 0x232c), Register('srsmap', 4, 0x2330), Register('cop0_reg13.3', 4, 0x2334), Register('cop0_reg14.3', 4, 0x2338), Register('cop0_reg15.3', 4, 0x233c), Register('config3', 4, 0x2340), Register('cop0_reg17.3', 4, 0x2344), Register('watchlo.3', 4, 0x2348), Register('watchhi.3', 4, 0x234c), Register('cop0_reg20.3', 4, 0x2350), Register('cop0_reg21.3', 4, 0x2354), Register('cop0_reg22.3', 4, 0x2358), Register('usertracedata', 4, 0x235c), Register('cop0_reg24.3', 4, 0x2360), Register('perfcnt.3', 4, 0x2364), Register('cop0_reg26.3', 4, 0x2368), Register('cacheerr.3', 4, 0x236c), Register('datalo.3', 4, 0x2370), Register('datahi.3', 4, 0x2374), Register('cop0_reg30.3', 4, 0x2378), Register('cop0_reg31.3', 4, 0x237c), Register('cop0_reg0.4', 4, 0x2400), Register('yqmask', 4, 0x2404), Register('tchalt', 4, 0x2408), Register('cop0_reg3.4', 4, 0x240c), Register('cop0_reg4.4', 4, 0x2410), Register('cop0_reg5.4', 4, 0x2414), Register('srsconf3', 4, 0x2418), Register('cop0_reg7.4', 4, 0x241c), Register('cop0_reg8.4', 4, 0x2420), Register('cop0_reg9.4', 4, 0x2424), Register('cop0_reg10.4', 4, 0x2428), Register('cop0_reg11.4', 4, 0x242c), Register('cop0_reg12.4', 4, 0x2430), Register('cop0_reg13.4', 4, 0x2434), Register('cop0_reg14.4', 4, 0x2438), Register('cop0_reg15.4', 4, 0x243c), Register('cop0_reg16.4', 4, 0x2440), Register('cop0_reg17.4', 4, 0x2444), Register('watchlo.4', 4, 0x2448), Register('watchhi.4', 4, 0x244c), Register('cop0_reg20.4', 4, 0x2450), Register('cop0_reg21.4', 4, 0x2454), Register('cop0_reg22.4', 4, 0x2458), Register('tracebpc', 4, 0x245c), Register('cop0_reg24.4', 4, 0x2460), Register('perfcnt.4', 4, 0x2464), Register('cop0_reg26.4', 4, 0x2468), Register('cacheerr.4', 4, 0x246c), Register('taglo.4', 4, 0x2470), Register('taghi.4', 4, 0x2474), Register('cop0_reg30.4', 4, 0x2478), Register('cop0_reg31.4', 4, 0x247c), Register('cop0_reg0.5', 4, 0x2500), Register('vpeschedule', 4, 0x2504), Register('tccontext', 4, 0x2508), Register('cop0_reg3.5', 4, 0x250c), Register('cop0_reg4.5', 4, 0x2510), Register('cop0_reg5.5', 4, 0x2514), Register('srsconf4', 4, 0x2518), Register('cop0_reg7.5', 4, 0x251c), Register('cop0_reg8.5', 4, 0x2520), Register('cop0_reg9.5', 4, 0x2524), Register('cop0_reg10.5', 4, 0x2528), Register('cop0_reg11.5', 4, 0x252c), Register('cop0_reg12.5', 4, 0x2530), Register('cop0_reg13.5', 4, 0x2534), Register('cop0_reg14.5', 4, 0x2538), Register('cop0_reg15.5', 4, 0x253c), Register('cop0_reg16.5', 4, 0x2540), Register('cop0_reg17.5', 4, 0x2544), Register('watchlo.5', 4, 0x2548), Register('watchhi.5', 4, 0x254c), Register('cop0_reg20.5', 4, 0x2550), Register('cop0_reg21.5', 4, 0x2554), Register('cop0_reg22.5', 4, 0x2558), Register('cop0_reg23.5', 4, 0x255c), Register('cop0_reg24.5', 4, 0x2560), Register('perfcnt.5', 4, 0x2564), Register('cop0_reg26.5', 4, 0x2568), Register('cacheerr.5', 4, 0x256c), Register('datalo.5', 4, 0x2570), Register('datahi.5', 4, 0x2574), Register('cop0_reg30.5', 4, 0x2578), Register('cop0_reg31.5', 4, 0x257c), Register('cop0_reg0.6', 4, 0x2600), Register('vpeschefback', 4, 0x2604), Register('tcschedule', 4, 0x2608), Register('cop0_reg3.6', 4, 0x260c), Register('cop0_reg4.6', 4, 0x2610), Register('cop0_reg5.6', 4, 0x2614), Register('cop0_reg6.6', 4, 0x2618), Register('cop0_reg7.6', 4, 0x261c), Register('cop0_reg8.6', 4, 0x2620), Register('cop0_reg9.6', 4, 0x2624), Register('cop0_reg10.6', 4, 0x2628), Register('cop0_reg11.6', 4, 0x262c), Register('cop0_reg12.6', 4, 0x2630), Register('cop0_reg13.6', 4, 0x2634), Register('cop0_reg14.6', 4, 0x2638), Register('cop0_reg15.6', 4, 0x263c), Register('cop0_reg16.6', 4, 0x2640), Register('cop0_reg17.6', 4, 0x2644), Register('watchlo.6', 4, 0x2648), Register('watchhi.6', 4, 0x264c), Register('cop0_reg20.6', 4, 0x2650), Register('cop0_reg21.6', 4, 0x2654), Register('cop0_reg22.6', 4, 0x2658), Register('cop0_reg23.6', 4, 0x265c), Register('cop0_reg24.6', 4, 0x2660), Register('perfcnt.6', 4, 0x2664), Register('cop0_reg26.6', 4, 0x2668), Register('cacheerr.6', 4, 0x266c), Register('taglo.6', 4, 0x2670), Register('taghi.6', 4, 0x2674), Register('cop0_reg30.6', 4, 0x2678), Register('cop0_reg31.6', 4, 0x267c), Register('cop0_reg0.7', 4, 0x2700), Register('vpeopt', 4, 0x2704), Register('tcschefback', 4, 0x2708), Register('cop0_reg3.7', 4, 0x270c), Register('cop0_reg4.7', 4, 0x2710), Register('cop0_reg5.7', 4, 0x2714), Register('cop0_reg6.7', 4, 0x2718), Register('cop0_reg7.7', 4, 0x271c), Register('cop0_reg8.7', 4, 0x2720), Register('cop0_reg9.7', 4, 0x2724), Register('cop0_reg10.7', 4, 0x2728), Register('cop0_reg11.7', 4, 0x272c), Register('cop0_reg12.7', 4, 0x2730), Register('cop0_reg13.7', 4, 0x2734), Register('cop0_reg14.7', 4, 0x2738), Register('cop0_reg15.7', 4, 0x273c), Register('cop0_reg16.7', 4, 0x2740), Register('cop0_reg17.7', 4, 0x2744), Register('watchlo.7', 4, 0x2748), Register('watchhi.7', 4, 0x274c), Register('cop0_reg20.7', 4, 0x2750), Register('cop0_reg21.7', 4, 0x2754), Register('cop0_reg22.7', 4, 0x2758), Register('cop0_reg23.7', 4, 0x275c), Register('cop0_reg24.7', 4, 0x2760), Register('perfcnt.7', 4, 0x2764), Register('cop0_reg26.7', 4, 0x2768), Register('cacheerr.7', 4, 0x276c), Register('datalo.7', 4, 0x2770), Register('datahi.7', 4, 0x2774), Register('cop0_reg30.7', 4, 0x2778), Register('cop0_reg31.7', 4, 0x277c), Register('hi', 4, 0x3000), Register('lo', 4, 0x3004), Register('hi1', 4, 0x3008), Register('lo1', 4, 0x300c), Register('hi2', 4, 0x3010), Register('lo2', 4, 0x3014), Register('hi3', 4, 0x3018), Register('lo3', 4, 0x301c), Register('tsp', 4, 0x3020), Register('isamodeswitch', 1, 0x3f00), Register('contextreg', 4, 0x4000) ]
class ArchPcode_tricore_LE_32_default(ArchPcode): name = 'tricore:LE:32:default' pcode_arch = 'tricore:LE:32:default' description = 'Siemens Tricore Embedded Processor' bits = 32 ip_offset = 0xfe08 sp_offset = 0xffa8 bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('contextreg', 4, 0x0), Register('task_asi', 4, 0x8004), Register('pma0', 4, 0x8100), Register('pma1', 4, 0x8104), Register('pma2', 4, 0x8108), Register('dcon2', 4, 0x9000), Register('dcon1', 4, 0x9008), Register('smacon', 4, 0x900c), Register('dstr', 4, 0x9010), Register('datr', 4, 0x9018), Register('deadd', 4, 0x901c), Register('diear', 4, 0x9020), Register('dietr', 4, 0x9024), Register('dcon0', 4, 0x9040), Register('pstr', 4, 0x9200), Register('pcon1', 4, 0x9204), Register('pcon2', 4, 0x9208), Register('pcon0', 4, 0x920c), Register('piear', 4, 0x9210), Register('pietr', 4, 0x9214), Register('compat', 4, 0x9400), Register('fpu_trap_con', 4, 0xa000), Register('fpu_trap_pc', 4, 0xa004), Register('fpu_trap_opc', 4, 0xa008), Register('fpu_trap_src1', 4, 0xa010), Register('fpu_trap_src2', 4, 0xa014), Register('fpu_trap_src3', 4, 0xa018), Register('dpr0_l', 4, 0xc000), Register('dpr0_u', 4, 0xc004), Register('dpr1_l', 4, 0xc008), Register('dpr1_u', 4, 0xc00c), Register('dpr2_l', 4, 0xc010), Register('dpr2_u', 4, 0xc014), Register('dpr3_l', 4, 0xc018), Register('dpr3_u', 4, 0xc01c), Register('dpr4_l', 4, 0xc020), Register('dpr4_u', 4, 0xc024), Register('dpr5_l', 4, 0xc028), Register('dpr5_u', 4, 0xc02c), Register('dpr6_l', 4, 0xc030), Register('dpr6_u', 4, 0xc034), Register('dpr7_l', 4, 0xc038), Register('dpr7_u', 4, 0xc03c), Register('dpr8_l', 4, 0xc040), Register('dpr8_u', 4, 0xc044), Register('dpr9_l', 4, 0xc048), Register('dpr9_u', 4, 0xc04c), Register('dpr10_l', 4, 0xc050), Register('dpr10_u', 4, 0xc054), Register('dpr11_l', 4, 0xc058), Register('dpr11_u', 4, 0xc05c), Register('dpr12_l', 4, 0xc060), Register('dpr12_u', 4, 0xc064), Register('dpr13_l', 4, 0xc068), Register('dpr13_u', 4, 0xc06c), Register('dpr14_l', 4, 0xc070), Register('dpr14_u', 4, 0xc074), Register('dpr15_l', 4, 0xc078), Register('dpr15_u', 4, 0xc07c), Register('cpr0_l', 4, 0xd000), Register('cpr0_u', 4, 0xd004), Register('cpr1_l', 4, 0xd008), Register('cpr1_u', 4, 0xd00c), Register('cpr2_l', 4, 0xd010), Register('cpr2_u', 4, 0xd014), Register('cpr3_l', 4, 0xd018), Register('cpr3_u', 4, 0xd01c), Register('cpr4_l', 4, 0xd020), Register('cpr4_u', 4, 0xd024), Register('cpr5_l', 4, 0xd028), Register('cpr5_u', 4, 0xd02c), Register('cpr6_l', 4, 0xd030), Register('cpr6_u', 4, 0xd034), Register('cpr7_l', 4, 0xd038), Register('cpr7_u', 4, 0xd03c), Register('cpr8_l', 4, 0xd040), Register('cpr8_u', 4, 0xd044), Register('cpr9_l', 4, 0xd048), Register('cpr9_u', 4, 0xd04c), Register('cpr10_l', 4, 0xd050), Register('cpr10_u', 4, 0xd054), Register('cpr11_l', 4, 0xd058), Register('cpr11_u', 4, 0xd05c), Register('cpr12_l', 4, 0xd060), Register('cpr12_u', 4, 0xd064), Register('cpr13_l', 4, 0xd068), Register('cpr13_u', 4, 0xd06c), Register('cpr14_l', 4, 0xd070), Register('cpr14_u', 4, 0xd074), Register('cpr15_l', 4, 0xd078), Register('cpr15_u', 4, 0xd07c), Register('cpxe_0', 4, 0xe000), Register('cpxe_1', 4, 0xe004), Register('cpxe_2', 4, 0xe008), Register('cpxe_3', 4, 0xe00c), Register('dpre_0', 4, 0xe010), Register('dpre_1', 4, 0xe014), Register('dpre_2', 4, 0xe018), Register('dpre_3', 4, 0xe01c), Register('dpwe_0', 4, 0xe020), Register('dpwe_1', 4, 0xe024), Register('dpwe_2', 4, 0xe028), Register('dpwe_3', 4, 0xe02c), Register('tps_con', 4, 0xe400), Register('tps_timer0', 4, 0xe404), Register('tps_timer1', 4, 0xe408), Register('tps_timer2', 4, 0xe40c), Register('tr0evt', 4, 0xf000), Register('tr0adr', 4, 0xf004), Register('tr1evt', 4, 0xf008), Register('tr1adr', 4, 0xf00c), Register('tr2evt', 4, 0xf010), Register('tra2dr', 4, 0xf014), Register('tr3evt', 4, 0xf018), Register('tr3adr', 4, 0xf01c), Register('tr4evt', 4, 0xf020), Register('tr4adr', 4, 0xf024), Register('tr5evt', 4, 0xf028), Register('tr5adr', 4, 0xf02c), Register('tr6evt', 4, 0xf030), Register('tr6adr', 4, 0xf034), Register('tr7evt', 4, 0xf038), Register('tr7adr', 4, 0xf03c), Register('cctrl', 4, 0xfc00), Register('ccnt', 4, 0xfc04), Register('icnt', 4, 0xfc08), Register('m1cnt', 4, 0xfc0c), Register('m2cnt', 4, 0xfc10), Register('m3cnt', 4, 0xfc14), Register('dbgsr', 4, 0xfd00), Register('exevt', 4, 0xfd08), Register('crevt', 4, 0xfd0c), Register('swevt', 4, 0xfd10), Register('trig_acc', 4, 0xfd30), Register('dms', 4, 0xfd40), Register('dcx', 4, 0xfd44), Register('dbgtcr', 4, 0xfd48), Register('pcxi', 4, 0xfe00), Register('psw', 4, 0xfe04), Register('pc', 4, 0xfe08, alias_names=('ip', )), Register('syscon', 4, 0xfe14), Register('cpu_id', 4, 0xfe18), Register('core_id', 4, 0xfe1c), Register('biv', 4, 0xfe20), Register('btv', 4, 0xfe24), Register('isp', 4, 0xfe28), Register('icr', 4, 0xfe2c), Register('pipn', 1, 0xfe2e), Register('fcx', 4, 0xfe38), Register('lcx', 4, 0xfe3c), Register('e0', 8, 0xff00), Register('d0', 4, 0xff00), Register('d1', 4, 0xff04), Register('e2', 8, 0xff08), Register('d2', 4, 0xff08), Register('d3', 4, 0xff0c), Register('e4', 8, 0xff10), Register('d4', 4, 0xff10), Register('d5', 4, 0xff14), Register('e6', 8, 0xff18), Register('d6', 4, 0xff18), Register('d7', 4, 0xff1c), Register('e8', 8, 0xff20), Register('d8', 4, 0xff20), Register('d9', 4, 0xff24), Register('e10', 8, 0xff28), Register('d10', 4, 0xff28), Register('d11', 4, 0xff2c), Register('e12', 8, 0xff30), Register('d12', 4, 0xff30), Register('d13', 4, 0xff34), Register('e14', 8, 0xff38), Register('d14', 4, 0xff38), Register('d15', 4, 0xff3c), Register('p0', 8, 0xff80), Register('a0', 4, 0xff80), Register('a1', 4, 0xff84), Register('p2', 8, 0xff88), Register('a2', 4, 0xff88), Register('a3', 4, 0xff8c), Register('p4', 8, 0xff90), Register('a4', 4, 0xff90), Register('a5', 4, 0xff94), Register('p6', 8, 0xff98), Register('a6', 4, 0xff98), Register('a7', 4, 0xff9c), Register('p8', 8, 0xffa0), Register('a8', 4, 0xffa0), Register('a9', 4, 0xffa4), Register('p10', 8, 0xffa8), Register('a10', 4, 0xffa8), Register('a11', 4, 0xffac), Register('p12', 8, 0xffb0), Register('a12', 4, 0xffb0), Register('a13', 4, 0xffb4), Register('p14', 8, 0xffb8), Register('a14', 4, 0xffb8), Register('a15', 4, 0xffbc), Register('r0', 4, 0xf0043f00), Register('r1', 4, 0xf0043f04), Register('r2', 4, 0xf0043f08), Register('r3', 4, 0xf0043f0c), Register('r4', 4, 0xf0043f10), Register('r5', 4, 0xf0043f14), Register('r6', 4, 0xf0043f18), Register('r7', 4, 0xf0043f1c) ]
class ArchPcode_6809_BE_16_default(ArchPcode): name = '6809:BE:16:default' pcode_arch = '6809:BE:16:default' description = '6809 Microprocessor' bits = 16 ip_offset = 0x10 sp_offset = 0x18 bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('d', 2, 0x0), Register('a', 1, 0x0), Register('b', 1, 0x1), Register('cc', 1, 0x8), Register('dp', 1, 0x9), Register('pc', 2, 0x10, alias_names=('ip', )), Register('x', 2, 0x12), Register('y', 2, 0x14), Register('u', 2, 0x16), Register('s', 2, 0x18), Register('exg16_r0', 2, 0x20), Register('exg8h_r0', 1, 0x20), Register('exg8l_r0', 1, 0x21), Register('exg16_r1', 2, 0x22), Register('exg8h_r1', 1, 0x22), Register('exg8l_r1', 1, 0x23) ]
class ArchRISCV(Arch): def __init__(self, endness="Iend_LE"): super(ArchRISCV, self).__init__(endness) self.call_pushes_ret = False self.branch_delay_slot = False sizeof = {'short': 16, 'int': 32, 'long': 32, 'long long': 64} function_prologs = {} function_epilogs = {} bits = 32 name = "RISCV" cs_arch = CS_ARCH_RISCV cs_mode = CS_MODE_RISCV32 instruction_endness = "Iend_LE" max_inst_bytes = 4 instruction_alignment = 4 persistent_regs = [] ret_instruction = b"\x00\x00\x80\x67" nop_instruction = b"\x13\x00\x00\x00" elf_tls = TLSArchInfo(1, 8, [], [0], [], 0, 0) register_list = [ Register(name="x0", size=4, alias_names=('zero', ), vex_offset=0, default_value=(0, False, 0)), Register(name='x1', size=4, alias_names=( 'ra', 'lr', ), general_purpose=True, vex_offset=4), Register(name='x2', size=4, alias_names=('sp', 'bp'), general_purpose=True, default_value=(Arch.initial_sp, True, 'global'), vex_offset=8), Register(name='x3', size=4, alias_names=('gp', ), general_purpose=True, vex_offset=12), Register(name='x4', size=4, alias_names=('tp', ), general_purpose=True, vex_offset=16), Register(name='x5', size=4, alias_names=('t0', ), general_purpose=True, vex_offset=20), Register(name='x6', size=4, alias_names=('t1', ), general_purpose=True, vex_offset=24), Register(name='x7', size=4, alias_names=('t2', ), general_purpose=True, vex_offset=28), Register(name='x8', size=4, alias_names=('s0', 'fp'), general_purpose=True, vex_offset=32), Register(name='x9', size=4, alias_names=('s1', ), general_purpose=True, vex_offset=36), Register(name='x10', size=4, alias_names=('a0', ), general_purpose=True, argument=True, vex_offset=40), Register(name='x11', size=4, alias_names=('a1', ), general_purpose=True, argument=True, vex_offset=44), Register(name='x12', size=4, alias_names=('a2', ), general_purpose=True, argument=True, vex_offset=48), Register(name='x13', size=4, alias_names=('a3', ), general_purpose=True, argument=True, vex_offset=52), Register(name='x14', size=4, alias_names=('a4', ), general_purpose=True, argument=True, vex_offset=56), Register(name='x15', size=4, alias_names=('a5', ), general_purpose=True, argument=True, vex_offset=60), Register(name='x16', size=4, alias_names=('a6', ), general_purpose=True, argument=True, vex_offset=64), Register(name='x17', size=4, alias_names=('a7', ), general_purpose=True, argument=True, vex_offset=68), Register(name='x18', size=4, alias_names=('s2', ), general_purpose=True, vex_offset=72), Register(name='x19', size=4, alias_names=('s3', ), general_purpose=True, vex_offset=76), Register(name='x20', size=4, alias_names=('s4', ), general_purpose=True, vex_offset=80), Register(name='x21', size=4, alias_names=('s5', ), general_purpose=True, vex_offset=84), Register(name='x22', size=4, alias_names=('s6', ), general_purpose=True, vex_offset=88), Register(name='x23', size=4, alias_names=('s7', ), general_purpose=True, vex_offset=92), Register(name='x24', size=4, alias_names=('s8', ), general_purpose=True, vex_offset=96), Register(name='x25', size=4, alias_names=('s9', ), general_purpose=True, vex_offset=100), Register(name='x26', size=4, alias_names=('s10', ), general_purpose=True, vex_offset=104), Register(name='x27', size=4, alias_names=('s11', ), general_purpose=True, vex_offset=108), Register(name='x28', size=4, alias_names=('t3', ), general_purpose=True, vex_offset=112), Register(name='x29', size=4, alias_names=('t4', ), general_purpose=True, vex_offset=116), Register(name='x30', size=4, alias_names=('t5', ), general_purpose=True, vex_offset=120), Register(name='x31', size=4, alias_names=('t6', ), general_purpose=True, vex_offset=124), Register(name='ip', alias_names={ 'pc', }, size=4, vex_offset=128), ]
class ArchPcode_avr8_LE_24_xmega(ArchPcode): name = 'avr8:LE:24:xmega' pcode_arch = 'avr8:LE:24:xmega' description = 'AVR8 for an Xmega' bits = 24 ip_offset = 0x42 sp_offset = 0x3d bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('r1r0', 2, 0x0), Register('r0', 1, 0x0), Register('r1', 1, 0x1), Register('r3r2', 2, 0x2), Register('r2', 1, 0x2), Register('r3', 1, 0x3), Register('r5r4', 2, 0x4), Register('r4', 1, 0x4), Register('r5', 1, 0x5), Register('r7r6', 2, 0x6), Register('r6', 1, 0x6), Register('r7', 1, 0x7), Register('r9r8', 2, 0x8), Register('r8', 1, 0x8), Register('r9', 1, 0x9), Register('r11r10', 2, 0xa), Register('r10', 1, 0xa), Register('r11', 1, 0xb), Register('r13r12', 2, 0xc), Register('r12', 1, 0xc), Register('r13', 1, 0xd), Register('r15r14', 2, 0xe), Register('r14', 1, 0xe), Register('r15', 1, 0xf), Register('r19r18r17r16', 4, 0x10), Register('r17r16', 2, 0x10), Register('r16', 1, 0x10), Register('r17', 1, 0x11), Register('r19r18', 2, 0x12), Register('r18', 1, 0x12), Register('r19', 1, 0x13), Register('r23r22r21r20', 4, 0x14), Register('r21r20', 2, 0x14), Register('r20', 1, 0x14), Register('r21', 1, 0x15), Register('r23r22', 2, 0x16), Register('r22', 1, 0x16), Register('r23', 1, 0x17), Register('w', 2, 0x18), Register('wlo', 1, 0x18), Register('whi', 1, 0x19), Register('x', 2, 0x1a), Register('xlo', 1, 0x1a), Register('xhi', 1, 0x1b), Register('y', 2, 0x1c), Register('ylo', 1, 0x1c), Register('yhi', 1, 0x1d), Register('z', 2, 0x1e), Register('zlo', 1, 0x1e), Register('zhi', 1, 0x1f), Register('sp', 2, 0x3d), Register('spl', 1, 0x3d), Register('sph', 1, 0x3e), Register('pc', 3, 0x42, alias_names=('ip',)), Register('cflg', 1, 0x80), Register('zflg', 1, 0x81), Register('nflg', 1, 0x82), Register('vflg', 1, 0x83), Register('sflg', 1, 0x84), Register('hflg', 1, 0x85), Register('tflg', 1, 0x86), Register('iflg', 1, 0x87), Register('skip', 1, 0x88), Register('contextreg', 4, 0x90), Register('rampd', 1, 0x38), Register('rampx', 1, 0x39), Register('rampy', 1, 0x3a), Register('rampz', 1, 0x3b), Register('eind', 1, 0x3c), Register('sreg', 1, 0x3f) ]
class ArchPcode_SuperH_BE_32_SH_2A(ArchPcode): name = 'SuperH:BE:32:SH-2A' pcode_arch = 'SuperH:BE:32:SH-2A' description = 'SuperH SH-2A processor 32-bit big-endian' bits = 32 ip_offset = 0x118 sp_offset = 0x3c bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('r0', 4, 0x0), Register('r1', 4, 0x4), Register('r2', 4, 0x8), Register('r3', 4, 0xc), Register('r4', 4, 0x10), Register('r5', 4, 0x14), Register('r6', 4, 0x18), Register('r7', 4, 0x1c), Register('r8', 4, 0x20), Register('r9', 4, 0x24), Register('r10', 4, 0x28), Register('r11', 4, 0x2c), Register('r12', 4, 0x30), Register('r13', 4, 0x34), Register('r14', 4, 0x38), Register('r15', 4, 0x3c), Register('sr', 4, 0x100), Register('gbr', 4, 0x104), Register('vbr', 4, 0x108), Register('mach', 4, 0x10c), Register('macl', 4, 0x110), Register('pr', 4, 0x114), Register('pc', 4, 0x118, alias_names=('ip', )), Register('tbr', 4, 0x180), Register('dr0', 8, 0x200), Register('fr0', 4, 0x200), Register('fr1', 4, 0x204), Register('dr2', 8, 0x208), Register('fr2', 4, 0x208), Register('fr3', 4, 0x20c), Register('dr4', 8, 0x210), Register('fr4', 4, 0x210), Register('fr5', 4, 0x214), Register('dr6', 8, 0x218), Register('fr6', 4, 0x218), Register('fr7', 4, 0x21c), Register('dr8', 8, 0x220), Register('fr8', 4, 0x220), Register('fr9', 4, 0x224), Register('dr10', 8, 0x228), Register('fr10', 4, 0x228), Register('fr11', 4, 0x22c), Register('dr12', 8, 0x230), Register('fr12', 4, 0x230), Register('fr13', 4, 0x234), Register('dr14', 8, 0x238), Register('fr14', 4, 0x238), Register('fr15', 4, 0x23c), Register('fpscr', 4, 0x300), Register('fpul', 4, 0x304), Register('resbank_base', 40960, 0x10000) ]
class ArchGameboy(Arch): bits = 24 name = "Gameboy" vex_arch = None instruction_alignment = 1 memory_endness = Endness.LE register_list = [ Register(name='af', size=2, vex_offset=0 ), Register(name='a', size=1, vex_offset=0 ), Register(name='f', size=1, vex_offset=8 ), Register(name='bc', size=2, vex_offset=16), Register(name='b', size=1, vex_offset=16), Register(name='c', size=1, vex_offset=24), Register(name='de', size=2, vex_offset=32), Register(name='d', size=1, vex_offset=32), Register(name='e', size=1, vex_offset=40), Register(name='hl', size=2, vex_offset=48), Register(name='h', size=1, vex_offset=48), Register(name='l', size=1, vex_offset=56), Register(name='sp', size=2, vex_offset=64), Register(name='pc', size=2, vex_offset=80), Register(name='ip', size=2, vex_offset=80), # Alias ] ip_offset = 10 sp_offset = 8 call_pushes_ret = True stack_change = -2 # bp_offset = 128 # Not used? default_register_values = [ ('pc', 0x100, False, None), ('sp', 0xFFFF, False, None) ] sizeof = {'short': 16, 'int': 16, 'long': 32, 'long long': 64} flags = { 'ZERO': 7, 'NEGATIVE': 6, 'HALF_CARRY': 5, 'CARRY': 4 } def __init__(self, endness=Endness.LE): super().__init__(endness)
class ArchPcode_z180_LE_16_default(ArchPcode): name = 'z180:LE:16:default' pcode_arch = 'z180:LE:16:default' description = 'Zilog Z180' bits = 16 ip_offset = 0x42 sp_offset = 0x44 bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('af', 2, 0x0), Register('f', 1, 0x0), Register('a', 1, 0x1), Register('bc', 2, 0x2), Register('c', 1, 0x2), Register('b', 1, 0x3), Register('de', 2, 0x4), Register('e', 1, 0x4), Register('d', 1, 0x5), Register('hl', 2, 0x6), Register('l', 1, 0x6), Register('h', 1, 0x7), Register('i', 1, 0x8), Register('r', 1, 0x9), Register('af_', 2, 0x20), Register('f_', 1, 0x20), Register('a_', 1, 0x21), Register('bc_', 2, 0x22), Register('c_', 1, 0x22), Register('b_', 1, 0x23), Register('de_', 2, 0x24), Register('e_', 1, 0x24), Register('d_', 1, 0x25), Register('hl_', 2, 0x26), Register('l_', 1, 0x26), Register('h_', 1, 0x27), Register('pc', 2, 0x42, alias_names=('ip', )), Register('sp', 2, 0x44), Register('ix', 2, 0x46), Register('iy', 2, 0x48), Register('rcbar', 1, 0x50), Register('rcbr', 1, 0x51), Register('rbbr', 1, 0x52), Register('decompile_mode', 1, 0x60), Register('contextreg', 4, 0xf0) ]
class ArchPcode_SuperH_BE_32_SH_1(ArchPcode): name = 'SuperH:BE:32:SH-1' pcode_arch = 'SuperH:BE:32:SH-1' description = 'SuperH SH-1 processor 32-bit big-endian' bits = 32 ip_offset = 0x118 sp_offset = 0x3c bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('r0', 4, 0x0), Register('r1', 4, 0x4), Register('r2', 4, 0x8), Register('r3', 4, 0xc), Register('r4', 4, 0x10), Register('r5', 4, 0x14), Register('r6', 4, 0x18), Register('r7', 4, 0x1c), Register('r8', 4, 0x20), Register('r9', 4, 0x24), Register('r10', 4, 0x28), Register('r11', 4, 0x2c), Register('r12', 4, 0x30), Register('r13', 4, 0x34), Register('r14', 4, 0x38), Register('r15', 4, 0x3c), Register('sr', 4, 0x100), Register('gbr', 4, 0x104), Register('vbr', 4, 0x108), Register('mach', 4, 0x10c), Register('macl', 4, 0x110), Register('pr', 4, 0x114), Register('pc', 4, 0x118, alias_names=('ip',)) ]
class ArchPcode_PIC_17_LE_16_PIC_17C7xx(ArchPcode): name = 'PIC-17:LE:16:PIC-17C7xx' pcode_arch = 'PIC-17:LE:16:PIC-17C7xx' description = 'PIC-17C7xx' bits = 16 ip_offset = 0x0 sp_offset = 0x4 bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('indf0', 1, 0x0), Register('fsr0', 1, 0x1), Register('pclat', 2, 0x2), Register('pcl', 1, 0x2), Register('pclath', 1, 0x3), Register('alusta', 1, 0x4), Register('t0sta', 1, 0x5), Register('cpusta', 1, 0x6), Register('intsta', 1, 0x7), Register('indf1', 1, 0x8), Register('fsr1', 1, 0x9), Register('tmr0l', 1, 0xb), Register('tmr0h', 1, 0xc), Register('tblptr', 2, 0xd), Register('tblptrl', 1, 0xd), Register('tblptrh', 1, 0xe), Register('bsr', 1, 0xf), Register('porta', 1, 0x10), Register('ddrb', 1, 0x11), Register('portb', 1, 0x12), Register('rcsta1', 1, 0x13), Register('rcreg1', 1, 0x14), Register('txsta1', 1, 0x15), Register('txreg1', 1, 0x16), Register('spbrg1', 1, 0x17), Register('prod', 2, 0x18), Register('prodl', 1, 0x18), Register('prodh', 1, 0x19), Register('ddrc', 1, 0x110), Register('portc', 1, 0x111), Register('ddrd', 1, 0x112), Register('portd', 1, 0x113), Register('ddre', 1, 0x114), Register('porte', 1, 0x115), Register('pir1', 1, 0x116), Register('pie1', 1, 0x117), Register('tmr1', 1, 0x210), Register('tmr2', 1, 0x211), Register('tmr3l', 1, 0x212), Register('tmr3h', 1, 0x213), Register('pr1', 1, 0x214), Register('pr2', 1, 0x215), Register('pr3lca1l', 1, 0x216), Register('pr3hca1h', 1, 0x217), Register('pw1dcl', 1, 0x310), Register('pw2dcl', 1, 0x311), Register('pw1dch', 1, 0x312), Register('pw2dch', 1, 0x313), Register('ca2l', 1, 0x314), Register('ca2h', 1, 0x315), Register('tcon1', 1, 0x316), Register('tcon2', 1, 0x317), Register('pir2', 1, 0x410), Register('pie2', 1, 0x411), Register('rcsta2', 1, 0x413), Register('rcreg2', 1, 0x414), Register('txsta2', 1, 0x415), Register('txreg2', 1, 0x416), Register('spbrg2', 1, 0x417), Register('ddrf', 1, 0x510), Register('portf', 1, 0x511), Register('ddrg', 1, 0x512), Register('portg', 1, 0x513), Register('adcon0', 1, 0x514), Register('adcon1', 1, 0x515), Register('adres', 2, 0x516), Register('adresl', 1, 0x516), Register('adresh', 1, 0x517), Register('sspadd', 1, 0x610), Register('sspcon1', 1, 0x611), Register('sspcon2', 1, 0x612), Register('sspstat', 1, 0x613), Register('sspbuf', 1, 0x614), Register('pw3dcl', 1, 0x710), Register('pw3dch', 1, 0x711), Register('ca3l', 1, 0x712), Register('ca3h', 1, 0x713), Register('ca4l', 1, 0x714), Register('ca4h', 1, 0x715), Register('tcon3', 1, 0x716), Register('ddrh', 1, 0x810), Register('porth', 1, 0x811), Register('ddrj', 1, 0x812), Register('portj', 1, 0x813), Register('pc', 2, 0x0, alias_names=('ip',)), Register('stkptr', 1, 0x4), Register('fs32', 1, 0x5), Register('fs10', 1, 0x6), Register('ov', 1, 0x7), Register('z', 1, 0x8), Register('dc', 1, 0x9), Register('c', 1, 0xa), Register('tblat', 2, 0x10), Register('tblatl', 1, 0x10), Register('tblath', 1, 0x11), Register('wreg', 1, 0x20) ]
class ArchPcode_x86_LE_16_Real_Mode(ArchPcode): name = 'x86:LE:16:Real Mode' pcode_arch = 'x86:LE:16:Real Mode' description = 'Intel/AMD 16-bit x86 Real Mode' bits = 16 ip_offset = 0x284 sp_offset = 0x10 bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('eax', 4, 0x0), Register('ax', 2, 0x0), Register('al', 1, 0x0), Register('ah', 1, 0x1), Register('ecx', 4, 0x4), Register('cx', 2, 0x4), Register('cl', 1, 0x4), Register('ch', 1, 0x5), Register('edx', 4, 0x8), Register('dx', 2, 0x8), Register('dl', 1, 0x8), Register('dh', 1, 0x9), Register('ebx', 4, 0xc), Register('bx', 2, 0xc), Register('bl', 1, 0xc), Register('bh', 1, 0xd), Register('esp', 4, 0x10), Register('sp', 2, 0x10), Register('ebp', 4, 0x14), Register('bp', 2, 0x14), Register('esi', 4, 0x18), Register('si', 2, 0x18), Register('edi', 4, 0x1c), Register('di', 2, 0x1c), Register('es', 2, 0x100), Register('cs', 2, 0x102), Register('ss', 2, 0x104), Register('ds', 2, 0x106), Register('fs', 2, 0x108), Register('gs', 2, 0x10a), Register('fs_offset', 4, 0x110), Register('gs_offset', 4, 0x114), Register('cf', 1, 0x200), Register('f1', 1, 0x201), Register('pf', 1, 0x202), Register('f3', 1, 0x203), Register('af', 1, 0x204), Register('f5', 1, 0x205), Register('zf', 1, 0x206), Register('sf', 1, 0x207), Register('tf', 1, 0x208), Register('if', 1, 0x209), Register('df', 1, 0x20a), Register('of', 1, 0x20b), Register('iopl', 1, 0x20c), Register('nt', 1, 0x20d), Register('f15', 1, 0x20e), Register('rf', 1, 0x20f), Register('vm', 1, 0x210), Register('ac', 1, 0x211), Register('vif', 1, 0x212), Register('vip', 1, 0x213), Register('id', 1, 0x214), Register('eflags', 4, 0x280), Register('flags', 2, 0x280), Register('eip', 4, 0x284, alias_names=('pc', 'ip')), Register('ip', 2, 0x284), Register('dr0', 4, 0x300), Register('dr1', 4, 0x304), Register('dr2', 4, 0x308), Register('dr3', 4, 0x30c), Register('dr4', 4, 0x310), Register('dr5', 4, 0x314), Register('dr6', 4, 0x318), Register('dr7', 4, 0x31c), Register('cr0', 4, 0x320), Register('cr2', 4, 0x328), Register('cr3', 4, 0x32c), Register('cr4', 4, 0x330), Register('tr0', 4, 0x400), Register('tr1', 4, 0x404), Register('tr2', 4, 0x408), Register('tr3', 4, 0x40c), Register('tr4', 4, 0x410), Register('tr5', 4, 0x414), Register('tr6', 4, 0x418), Register('tr7', 4, 0x41c), Register('xcr0', 8, 0x600), Register('bndcfgs', 8, 0x700), Register('bndcfgu', 8, 0x708), Register('bndstatus', 8, 0x710), Register('bnd0', 16, 0x740), Register('bnd0_lb', 8, 0x740), Register('bnd0_ub', 8, 0x748), Register('bnd1', 16, 0x750), Register('bnd1_lb', 8, 0x750), Register('bnd1_ub', 8, 0x758), Register('bnd2', 16, 0x760), Register('bnd2_lb', 8, 0x760), Register('bnd2_ub', 8, 0x768), Register('bnd3', 16, 0x770), Register('bnd3_lb', 8, 0x770), Register('bnd3_ub', 8, 0x778), Register('ssp', 8, 0x7c0), Register('ia32_pl2_ssp', 8, 0x7c8), Register('ia32_pl1_ssp', 8, 0x7d0), Register('ia32_pl0_ssp', 8, 0x7d8), Register('st0', 10, 0x1000), Register('st1', 10, 0x100a), Register('st2', 10, 0x1014), Register('st3', 10, 0x101e), Register('st4', 10, 0x1028), Register('st5', 10, 0x1032), Register('st6', 10, 0x103c), Register('st7', 10, 0x1046), Register('c0', 1, 0x1080), Register('c1', 1, 0x1081), Register('c2', 1, 0x1082), Register('c3', 1, 0x1083), Register('mxcsr', 4, 0x1084), Register('fpucontrolword', 2, 0x1090), Register('fpustatusword', 2, 0x1092), Register('fputagword', 2, 0x1094), Register('fpulastinstructionopcode', 2, 0x1096), Register('fpudatapointer', 4, 0x1098), Register('fpuinstructionpointer', 4, 0x109c), Register('mm0', 8, 0x1100), Register('mm0_da', 4, 0x1100), Register('mm0_wa', 2, 0x1100), Register('mm0_ba', 1, 0x1100), Register('mm0_bb', 1, 0x1101), Register('mm0_wb', 2, 0x1102), Register('mm0_bc', 1, 0x1102), Register('mm0_bd', 1, 0x1103), Register('mm0_db', 4, 0x1104), Register('mm0_wc', 2, 0x1104), Register('mm0_be', 1, 0x1104), Register('mm0_bf', 1, 0x1105), Register('mm0_wd', 2, 0x1106), Register('mm0_bg', 1, 0x1106), Register('mm0_bh', 1, 0x1107), Register('mm1', 8, 0x1108), Register('mm1_da', 4, 0x1108), Register('mm1_wa', 2, 0x1108), Register('mm1_ba', 1, 0x1108), Register('mm1_bb', 1, 0x1109), Register('mm1_wb', 2, 0x110a), Register('mm1_bc', 1, 0x110a), Register('mm1_bd', 1, 0x110b), Register('mm1_db', 4, 0x110c), Register('mm1_wc', 2, 0x110c), Register('mm1_be', 1, 0x110c), Register('mm1_bf', 1, 0x110d), Register('mm1_wd', 2, 0x110e), Register('mm1_bg', 1, 0x110e), Register('mm1_bh', 1, 0x110f), Register('mm2', 8, 0x1110), Register('mm2_da', 4, 0x1110), Register('mm2_wa', 2, 0x1110), Register('mm2_ba', 1, 0x1110), Register('mm2_bb', 1, 0x1111), Register('mm2_wb', 2, 0x1112), Register('mm2_bc', 1, 0x1112), Register('mm2_bd', 1, 0x1113), Register('mm2_db', 4, 0x1114), Register('mm2_wc', 2, 0x1114), Register('mm2_be', 1, 0x1114), Register('mm2_bf', 1, 0x1115), Register('mm2_wd', 2, 0x1116), Register('mm2_bg', 1, 0x1116), Register('mm2_bh', 1, 0x1117), Register('mm3', 8, 0x1118), Register('mm3_da', 4, 0x1118), Register('mm3_wa', 2, 0x1118), Register('mm3_ba', 1, 0x1118), Register('mm3_bb', 1, 0x1119), Register('mm3_wb', 2, 0x111a), Register('mm3_bc', 1, 0x111a), Register('mm3_bd', 1, 0x111b), Register('mm3_db', 4, 0x111c), Register('mm3_wc', 2, 0x111c), Register('mm3_be', 1, 0x111c), Register('mm3_bf', 1, 0x111d), Register('mm3_wd', 2, 0x111e), Register('mm3_bg', 1, 0x111e), Register('mm3_bh', 1, 0x111f), Register('mm4', 8, 0x1120), Register('mm4_da', 4, 0x1120), Register('mm4_wa', 2, 0x1120), Register('mm4_ba', 1, 0x1120), Register('mm4_bb', 1, 0x1121), Register('mm4_wb', 2, 0x1122), Register('mm4_bc', 1, 0x1122), Register('mm4_bd', 1, 0x1123), Register('mm4_db', 4, 0x1124), Register('mm4_wc', 2, 0x1124), Register('mm4_be', 1, 0x1124), Register('mm4_bf', 1, 0x1125), Register('mm4_wd', 2, 0x1126), Register('mm4_bg', 1, 0x1126), Register('mm4_bh', 1, 0x1127), Register('mm5', 8, 0x1128), Register('mm5_da', 4, 0x1128), Register('mm5_wa', 2, 0x1128), Register('mm5_ba', 1, 0x1128), Register('mm5_bb', 1, 0x1129), Register('mm5_wb', 2, 0x112a), Register('mm5_bc', 1, 0x112a), Register('mm5_bd', 1, 0x112b), Register('mm5_db', 4, 0x112c), Register('mm5_wc', 2, 0x112c), Register('mm5_be', 1, 0x112c), Register('mm5_bf', 1, 0x112d), Register('mm5_wd', 2, 0x112e), Register('mm5_bg', 1, 0x112e), Register('mm5_bh', 1, 0x112f), Register('mm6', 8, 0x1130), Register('mm6_da', 4, 0x1130), Register('mm6_wa', 2, 0x1130), Register('mm6_ba', 1, 0x1130), Register('mm6_bb', 1, 0x1131), Register('mm6_wb', 2, 0x1132), Register('mm6_bc', 1, 0x1132), Register('mm6_bd', 1, 0x1133), Register('mm6_db', 4, 0x1134), Register('mm6_wc', 2, 0x1134), Register('mm6_be', 1, 0x1134), Register('mm6_bf', 1, 0x1135), Register('mm6_wd', 2, 0x1136), Register('mm6_bg', 1, 0x1136), Register('mm6_bh', 1, 0x1137), Register('mm7', 8, 0x1138), Register('mm7_da', 4, 0x1138), Register('mm7_wa', 2, 0x1138), Register('mm7_ba', 1, 0x1138), Register('mm7_bb', 1, 0x1139), Register('mm7_wb', 2, 0x113a), Register('mm7_bc', 1, 0x113a), Register('mm7_bd', 1, 0x113b), Register('mm7_db', 4, 0x113c), Register('mm7_wc', 2, 0x113c), Register('mm7_be', 1, 0x113c), Register('mm7_bf', 1, 0x113d), Register('mm7_wd', 2, 0x113e), Register('mm7_bg', 1, 0x113e), Register('mm7_bh', 1, 0x113f), Register('ymm0', 32, 0x1200), Register('xmm0', 16, 0x1200), Register('xmm0_qa', 8, 0x1200), Register('xmm0_da', 4, 0x1200), Register('xmm0_wa', 2, 0x1200), Register('xmm0_ba', 1, 0x1200), Register('xmm0_bb', 1, 0x1201), Register('xmm0_wb', 2, 0x1202), Register('xmm0_bc', 1, 0x1202), Register('xmm0_bd', 1, 0x1203), Register('xmm0_db', 4, 0x1204), Register('xmm0_wc', 2, 0x1204), Register('xmm0_be', 1, 0x1204), Register('xmm0_bf', 1, 0x1205), Register('xmm0_wd', 2, 0x1206), Register('xmm0_bg', 1, 0x1206), Register('xmm0_bh', 1, 0x1207), Register('xmm0_qb', 8, 0x1208), Register('xmm0_dc', 4, 0x1208), Register('xmm0_we', 2, 0x1208), Register('xmm0_bi', 1, 0x1208), Register('xmm0_bj', 1, 0x1209), Register('xmm0_wf', 2, 0x120a), Register('xmm0_bk', 1, 0x120a), Register('xmm0_bl', 1, 0x120b), Register('xmm0_dd', 4, 0x120c), Register('xmm0_wg', 2, 0x120c), Register('xmm0_bm', 1, 0x120c), Register('xmm0_bn', 1, 0x120d), Register('xmm0_wh', 2, 0x120e), Register('xmm0_bo', 1, 0x120e), Register('xmm0_bp', 1, 0x120f), Register('ymm0_h', 16, 0x1210), Register('ymm1', 32, 0x1220), Register('xmm1', 16, 0x1220), Register('xmm1_qa', 8, 0x1220), Register('xmm1_da', 4, 0x1220), Register('xmm1_wa', 2, 0x1220), Register('xmm1_ba', 1, 0x1220), Register('xmm1_bb', 1, 0x1221), Register('xmm1_wb', 2, 0x1222), Register('xmm1_bc', 1, 0x1222), Register('xmm1_bd', 1, 0x1223), Register('xmm1_db', 4, 0x1224), Register('xmm1_wc', 2, 0x1224), Register('xmm1_be', 1, 0x1224), Register('xmm1_bf', 1, 0x1225), Register('xmm1_wd', 2, 0x1226), Register('xmm1_bg', 1, 0x1226), Register('xmm1_bh', 1, 0x1227), Register('xmm1_qb', 8, 0x1228), Register('xmm1_dc', 4, 0x1228), Register('xmm1_we', 2, 0x1228), Register('xmm1_bi', 1, 0x1228), Register('xmm1_bj', 1, 0x1229), Register('xmm1_wf', 2, 0x122a), Register('xmm1_bk', 1, 0x122a), Register('xmm1_bl', 1, 0x122b), Register('xmm1_dd', 4, 0x122c), Register('xmm1_wg', 2, 0x122c), Register('xmm1_bm', 1, 0x122c), Register('xmm1_bn', 1, 0x122d), Register('xmm1_wh', 2, 0x122e), Register('xmm1_bo', 1, 0x122e), Register('xmm1_bp', 1, 0x122f), Register('ymm1_h', 16, 0x1230), Register('ymm2', 32, 0x1240), Register('xmm2', 16, 0x1240), Register('xmm2_qa', 8, 0x1240), Register('xmm2_da', 4, 0x1240), Register('xmm2_wa', 2, 0x1240), Register('xmm2_ba', 1, 0x1240), Register('xmm2_bb', 1, 0x1241), Register('xmm2_wb', 2, 0x1242), Register('xmm2_bc', 1, 0x1242), Register('xmm2_bd', 1, 0x1243), Register('xmm2_db', 4, 0x1244), Register('xmm2_wc', 2, 0x1244), Register('xmm2_be', 1, 0x1244), Register('xmm2_bf', 1, 0x1245), Register('xmm2_wd', 2, 0x1246), Register('xmm2_bg', 1, 0x1246), Register('xmm2_bh', 1, 0x1247), Register('xmm2_qb', 8, 0x1248), Register('xmm2_dc', 4, 0x1248), Register('xmm2_we', 2, 0x1248), Register('xmm2_bi', 1, 0x1248), Register('xmm2_bj', 1, 0x1249), Register('xmm2_wf', 2, 0x124a), Register('xmm2_bk', 1, 0x124a), Register('xmm2_bl', 1, 0x124b), Register('xmm2_dd', 4, 0x124c), Register('xmm2_wg', 2, 0x124c), Register('xmm2_bm', 1, 0x124c), Register('xmm2_bn', 1, 0x124d), Register('xmm2_wh', 2, 0x124e), Register('xmm2_bo', 1, 0x124e), Register('xmm2_bp', 1, 0x124f), Register('ymm2_h', 16, 0x1250), Register('ymm3', 32, 0x1260), Register('xmm3', 16, 0x1260), Register('xmm3_qa', 8, 0x1260), Register('xmm3_da', 4, 0x1260), Register('xmm3_wa', 2, 0x1260), Register('xmm3_ba', 1, 0x1260), Register('xmm3_bb', 1, 0x1261), Register('xmm3_wb', 2, 0x1262), Register('xmm3_bc', 1, 0x1262), Register('xmm3_bd', 1, 0x1263), Register('xmm3_db', 4, 0x1264), Register('xmm3_wc', 2, 0x1264), Register('xmm3_be', 1, 0x1264), Register('xmm3_bf', 1, 0x1265), Register('xmm3_wd', 2, 0x1266), Register('xmm3_bg', 1, 0x1266), Register('xmm3_bh', 1, 0x1267), Register('xmm3_qb', 8, 0x1268), Register('xmm3_dc', 4, 0x1268), Register('xmm3_we', 2, 0x1268), Register('xmm3_bi', 1, 0x1268), Register('xmm3_bj', 1, 0x1269), Register('xmm3_wf', 2, 0x126a), Register('xmm3_bk', 1, 0x126a), Register('xmm3_bl', 1, 0x126b), Register('xmm3_dd', 4, 0x126c), Register('xmm3_wg', 2, 0x126c), Register('xmm3_bm', 1, 0x126c), Register('xmm3_bn', 1, 0x126d), Register('xmm3_wh', 2, 0x126e), Register('xmm3_bo', 1, 0x126e), Register('xmm3_bp', 1, 0x126f), Register('ymm3_h', 16, 0x1270), Register('ymm4', 32, 0x1280), Register('xmm4', 16, 0x1280), Register('xmm4_qa', 8, 0x1280), Register('xmm4_da', 4, 0x1280), Register('xmm4_wa', 2, 0x1280), Register('xmm4_ba', 1, 0x1280), Register('xmm4_bb', 1, 0x1281), Register('xmm4_wb', 2, 0x1282), Register('xmm4_bc', 1, 0x1282), Register('xmm4_bd', 1, 0x1283), Register('xmm4_db', 4, 0x1284), Register('xmm4_wc', 2, 0x1284), Register('xmm4_be', 1, 0x1284), Register('xmm4_bf', 1, 0x1285), Register('xmm4_wd', 2, 0x1286), Register('xmm4_bg', 1, 0x1286), Register('xmm4_bh', 1, 0x1287), Register('xmm4_qb', 8, 0x1288), Register('xmm4_dc', 4, 0x1288), Register('xmm4_we', 2, 0x1288), Register('xmm4_bi', 1, 0x1288), Register('xmm4_bj', 1, 0x1289), Register('xmm4_wf', 2, 0x128a), Register('xmm4_bk', 1, 0x128a), Register('xmm4_bl', 1, 0x128b), Register('xmm4_dd', 4, 0x128c), Register('xmm4_wg', 2, 0x128c), Register('xmm4_bm', 1, 0x128c), Register('xmm4_bn', 1, 0x128d), Register('xmm4_wh', 2, 0x128e), Register('xmm4_bo', 1, 0x128e), Register('xmm4_bp', 1, 0x128f), Register('ymm4_h', 16, 0x1290), Register('ymm5', 32, 0x12a0), Register('xmm5', 16, 0x12a0), Register('xmm5_qa', 8, 0x12a0), Register('xmm5_da', 4, 0x12a0), Register('xmm5_wa', 2, 0x12a0), Register('xmm5_ba', 1, 0x12a0), Register('xmm5_bb', 1, 0x12a1), Register('xmm5_wb', 2, 0x12a2), Register('xmm5_bc', 1, 0x12a2), Register('xmm5_bd', 1, 0x12a3), Register('xmm5_db', 4, 0x12a4), Register('xmm5_wc', 2, 0x12a4), Register('xmm5_be', 1, 0x12a4), Register('xmm5_bf', 1, 0x12a5), Register('xmm5_wd', 2, 0x12a6), Register('xmm5_bg', 1, 0x12a6), Register('xmm5_bh', 1, 0x12a7), Register('xmm5_qb', 8, 0x12a8), Register('xmm5_dc', 4, 0x12a8), Register('xmm5_we', 2, 0x12a8), Register('xmm5_bi', 1, 0x12a8), Register('xmm5_bj', 1, 0x12a9), Register('xmm5_wf', 2, 0x12aa), Register('xmm5_bk', 1, 0x12aa), Register('xmm5_bl', 1, 0x12ab), Register('xmm5_dd', 4, 0x12ac), Register('xmm5_wg', 2, 0x12ac), Register('xmm5_bm', 1, 0x12ac), Register('xmm5_bn', 1, 0x12ad), Register('xmm5_wh', 2, 0x12ae), Register('xmm5_bo', 1, 0x12ae), Register('xmm5_bp', 1, 0x12af), Register('ymm5_h', 16, 0x12b0), Register('ymm6', 32, 0x12c0), Register('xmm6', 16, 0x12c0), Register('xmm6_qa', 8, 0x12c0), Register('xmm6_da', 4, 0x12c0), Register('xmm6_wa', 2, 0x12c0), Register('xmm6_ba', 1, 0x12c0), Register('xmm6_bb', 1, 0x12c1), Register('xmm6_wb', 2, 0x12c2), Register('xmm6_bc', 1, 0x12c2), Register('xmm6_bd', 1, 0x12c3), Register('xmm6_db', 4, 0x12c4), Register('xmm6_wc', 2, 0x12c4), Register('xmm6_be', 1, 0x12c4), Register('xmm6_bf', 1, 0x12c5), Register('xmm6_wd', 2, 0x12c6), Register('xmm6_bg', 1, 0x12c6), Register('xmm6_bh', 1, 0x12c7), Register('xmm6_qb', 8, 0x12c8), Register('xmm6_dc', 4, 0x12c8), Register('xmm6_we', 2, 0x12c8), Register('xmm6_bi', 1, 0x12c8), Register('xmm6_bj', 1, 0x12c9), Register('xmm6_wf', 2, 0x12ca), Register('xmm6_bk', 1, 0x12ca), Register('xmm6_bl', 1, 0x12cb), Register('xmm6_dd', 4, 0x12cc), Register('xmm6_wg', 2, 0x12cc), Register('xmm6_bm', 1, 0x12cc), Register('xmm6_bn', 1, 0x12cd), Register('xmm6_wh', 2, 0x12ce), Register('xmm6_bo', 1, 0x12ce), Register('xmm6_bp', 1, 0x12cf), Register('ymm6_h', 16, 0x12d0), Register('ymm7', 32, 0x12e0), Register('xmm7', 16, 0x12e0), Register('xmm7_qa', 8, 0x12e0), Register('xmm7_da', 4, 0x12e0), Register('xmm7_wa', 2, 0x12e0), Register('xmm7_ba', 1, 0x12e0), Register('xmm7_bb', 1, 0x12e1), Register('xmm7_wb', 2, 0x12e2), Register('xmm7_bc', 1, 0x12e2), Register('xmm7_bd', 1, 0x12e3), Register('xmm7_db', 4, 0x12e4), Register('xmm7_wc', 2, 0x12e4), Register('xmm7_be', 1, 0x12e4), Register('xmm7_bf', 1, 0x12e5), Register('xmm7_wd', 2, 0x12e6), Register('xmm7_bg', 1, 0x12e6), Register('xmm7_bh', 1, 0x12e7), Register('xmm7_qb', 8, 0x12e8), Register('xmm7_dc', 4, 0x12e8), Register('xmm7_we', 2, 0x12e8), Register('xmm7_bi', 1, 0x12e8), Register('xmm7_bj', 1, 0x12e9), Register('xmm7_wf', 2, 0x12ea), Register('xmm7_bk', 1, 0x12ea), Register('xmm7_bl', 1, 0x12eb), Register('xmm7_dd', 4, 0x12ec), Register('xmm7_wg', 2, 0x12ec), Register('xmm7_bm', 1, 0x12ec), Register('xmm7_bn', 1, 0x12ed), Register('xmm7_wh', 2, 0x12ee), Register('xmm7_bo', 1, 0x12ee), Register('xmm7_bp', 1, 0x12ef), Register('ymm7_h', 16, 0x12f0), Register('ymm8', 32, 0x1300), Register('xmm8', 16, 0x1300), Register('xmm8_qa', 8, 0x1300), Register('xmm8_da', 4, 0x1300), Register('xmm8_wa', 2, 0x1300), Register('xmm8_ba', 1, 0x1300), Register('xmm8_bb', 1, 0x1301), Register('xmm8_wb', 2, 0x1302), Register('xmm8_bc', 1, 0x1302), Register('xmm8_bd', 1, 0x1303), Register('xmm8_db', 4, 0x1304), Register('xmm8_wc', 2, 0x1304), Register('xmm8_be', 1, 0x1304), Register('xmm8_bf', 1, 0x1305), Register('xmm8_wd', 2, 0x1306), Register('xmm8_bg', 1, 0x1306), Register('xmm8_bh', 1, 0x1307), Register('xmm8_qb', 8, 0x1308), Register('xmm8_dc', 4, 0x1308), Register('xmm8_we', 2, 0x1308), Register('xmm8_bi', 1, 0x1308), Register('xmm8_bj', 1, 0x1309), Register('xmm8_wf', 2, 0x130a), Register('xmm8_bk', 1, 0x130a), Register('xmm8_bl', 1, 0x130b), Register('xmm8_dd', 4, 0x130c), Register('xmm8_wg', 2, 0x130c), Register('xmm8_bm', 1, 0x130c), Register('xmm8_bn', 1, 0x130d), Register('xmm8_wh', 2, 0x130e), Register('xmm8_bo', 1, 0x130e), Register('xmm8_bp', 1, 0x130f), Register('ymm8_h', 16, 0x1310), Register('ymm9', 32, 0x1320), Register('xmm9', 16, 0x1320), Register('xmm9_qa', 8, 0x1320), Register('xmm9_da', 4, 0x1320), Register('xmm9_wa', 2, 0x1320), Register('xmm9_ba', 1, 0x1320), Register('xmm9_bb', 1, 0x1321), Register('xmm9_wb', 2, 0x1322), Register('xmm9_bc', 1, 0x1322), Register('xmm9_bd', 1, 0x1323), Register('xmm9_db', 4, 0x1324), Register('xmm9_wc', 2, 0x1324), Register('xmm9_be', 1, 0x1324), Register('xmm9_bf', 1, 0x1325), Register('xmm9_wd', 2, 0x1326), Register('xmm9_bg', 1, 0x1326), Register('xmm9_bh', 1, 0x1327), Register('xmm9_qb', 8, 0x1328), Register('xmm9_dc', 4, 0x1328), Register('xmm9_we', 2, 0x1328), Register('xmm9_bi', 1, 0x1328), Register('xmm9_bj', 1, 0x1329), Register('xmm9_wf', 2, 0x132a), Register('xmm9_bk', 1, 0x132a), Register('xmm9_bl', 1, 0x132b), Register('xmm9_dd', 4, 0x132c), Register('xmm9_wg', 2, 0x132c), Register('xmm9_bm', 1, 0x132c), Register('xmm9_bn', 1, 0x132d), Register('xmm9_wh', 2, 0x132e), Register('xmm9_bo', 1, 0x132e), Register('xmm9_bp', 1, 0x132f), Register('ymm9_h', 16, 0x1330), Register('ymm10', 32, 0x1340), Register('xmm10', 16, 0x1340), Register('xmm10_qa', 8, 0x1340), Register('xmm10_da', 4, 0x1340), Register('xmm10_wa', 2, 0x1340), Register('xmm10_ba', 1, 0x1340), Register('xmm10_bb', 1, 0x1341), Register('xmm10_wb', 2, 0x1342), Register('xmm10_bc', 1, 0x1342), Register('xmm10_bd', 1, 0x1343), Register('xmm10_db', 4, 0x1344), Register('xmm10_wc', 2, 0x1344), Register('xmm10_be', 1, 0x1344), Register('xmm10_bf', 1, 0x1345), Register('xmm10_wd', 2, 0x1346), Register('xmm10_bg', 1, 0x1346), Register('xmm10_bh', 1, 0x1347), Register('xmm10_qb', 8, 0x1348), Register('xmm10_dc', 4, 0x1348), Register('xmm10_we', 2, 0x1348), Register('xmm10_bi', 1, 0x1348), Register('xmm10_bj', 1, 0x1349), Register('xmm10_wf', 2, 0x134a), Register('xmm10_bk', 1, 0x134a), Register('xmm10_bl', 1, 0x134b), Register('xmm10_dd', 4, 0x134c), Register('xmm10_wg', 2, 0x134c), Register('xmm10_bm', 1, 0x134c), Register('xmm10_bn', 1, 0x134d), Register('xmm10_wh', 2, 0x134e), Register('xmm10_bo', 1, 0x134e), Register('xmm10_bp', 1, 0x134f), Register('ymm10_h', 16, 0x1350), Register('ymm11', 32, 0x1360), Register('xmm11', 16, 0x1360), Register('xmm11_qa', 8, 0x1360), Register('xmm11_da', 4, 0x1360), Register('xmm11_wa', 2, 0x1360), Register('xmm11_ba', 1, 0x1360), Register('xmm11_bb', 1, 0x1361), Register('xmm11_wb', 2, 0x1362), Register('xmm11_bc', 1, 0x1362), Register('xmm11_bd', 1, 0x1363), Register('xmm11_db', 4, 0x1364), Register('xmm11_wc', 2, 0x1364), Register('xmm11_be', 1, 0x1364), Register('xmm11_bf', 1, 0x1365), Register('xmm11_wd', 2, 0x1366), Register('xmm11_bg', 1, 0x1366), Register('xmm11_bh', 1, 0x1367), Register('xmm11_qb', 8, 0x1368), Register('xmm11_dc', 4, 0x1368), Register('xmm11_we', 2, 0x1368), Register('xmm11_bi', 1, 0x1368), Register('xmm11_bj', 1, 0x1369), Register('xmm11_wf', 2, 0x136a), Register('xmm11_bk', 1, 0x136a), Register('xmm11_bl', 1, 0x136b), Register('xmm11_dd', 4, 0x136c), Register('xmm11_wg', 2, 0x136c), Register('xmm11_bm', 1, 0x136c), Register('xmm11_bn', 1, 0x136d), Register('xmm11_wh', 2, 0x136e), Register('xmm11_bo', 1, 0x136e), Register('xmm11_bp', 1, 0x136f), Register('ymm11_h', 16, 0x1370), Register('ymm12', 32, 0x1380), Register('xmm12', 16, 0x1380), Register('xmm12_qa', 8, 0x1380), Register('xmm12_da', 4, 0x1380), Register('xmm12_wa', 2, 0x1380), Register('xmm12_ba', 1, 0x1380), Register('xmm12_bb', 1, 0x1381), Register('xmm12_wb', 2, 0x1382), Register('xmm12_bc', 1, 0x1382), Register('xmm12_bd', 1, 0x1383), Register('xmm12_db', 4, 0x1384), Register('xmm12_wc', 2, 0x1384), Register('xmm12_be', 1, 0x1384), Register('xmm12_bf', 1, 0x1385), Register('xmm12_wd', 2, 0x1386), Register('xmm12_bg', 1, 0x1386), Register('xmm12_bh', 1, 0x1387), Register('xmm12_qb', 8, 0x1388), Register('xmm12_dc', 4, 0x1388), Register('xmm12_we', 2, 0x1388), Register('xmm12_bi', 1, 0x1388), Register('xmm12_bj', 1, 0x1389), Register('xmm12_wf', 2, 0x138a), Register('xmm12_bk', 1, 0x138a), Register('xmm12_bl', 1, 0x138b), Register('xmm12_dd', 4, 0x138c), Register('xmm12_wg', 2, 0x138c), Register('xmm12_bm', 1, 0x138c), Register('xmm12_bn', 1, 0x138d), Register('xmm12_wh', 2, 0x138e), Register('xmm12_bo', 1, 0x138e), Register('xmm12_bp', 1, 0x138f), Register('ymm12_h', 16, 0x1390), Register('ymm13', 32, 0x13a0), Register('xmm13', 16, 0x13a0), Register('xmm13_qa', 8, 0x13a0), Register('xmm13_da', 4, 0x13a0), Register('xmm13_wa', 2, 0x13a0), Register('xmm13_ba', 1, 0x13a0), Register('xmm13_bb', 1, 0x13a1), Register('xmm13_wb', 2, 0x13a2), Register('xmm13_bc', 1, 0x13a2), Register('xmm13_bd', 1, 0x13a3), Register('xmm13_db', 4, 0x13a4), Register('xmm13_wc', 2, 0x13a4), Register('xmm13_be', 1, 0x13a4), Register('xmm13_bf', 1, 0x13a5), Register('xmm13_wd', 2, 0x13a6), Register('xmm13_bg', 1, 0x13a6), Register('xmm13_bh', 1, 0x13a7), Register('xmm13_qb', 8, 0x13a8), Register('xmm13_dc', 4, 0x13a8), Register('xmm13_we', 2, 0x13a8), Register('xmm13_bi', 1, 0x13a8), Register('xmm13_bj', 1, 0x13a9), Register('xmm13_wf', 2, 0x13aa), Register('xmm13_bk', 1, 0x13aa), Register('xmm13_bl', 1, 0x13ab), Register('xmm13_dd', 4, 0x13ac), Register('xmm13_wg', 2, 0x13ac), Register('xmm13_bm', 1, 0x13ac), Register('xmm13_bn', 1, 0x13ad), Register('xmm13_wh', 2, 0x13ae), Register('xmm13_bo', 1, 0x13ae), Register('xmm13_bp', 1, 0x13af), Register('ymm13_h', 16, 0x13b0), Register('ymm14', 32, 0x13c0), Register('xmm14', 16, 0x13c0), Register('xmm14_qa', 8, 0x13c0), Register('xmm14_da', 4, 0x13c0), Register('xmm14_wa', 2, 0x13c0), Register('xmm14_ba', 1, 0x13c0), Register('xmm14_bb', 1, 0x13c1), Register('xmm14_wb', 2, 0x13c2), Register('xmm14_bc', 1, 0x13c2), Register('xmm14_bd', 1, 0x13c3), Register('xmm14_db', 4, 0x13c4), Register('xmm14_wc', 2, 0x13c4), Register('xmm14_be', 1, 0x13c4), Register('xmm14_bf', 1, 0x13c5), Register('xmm14_wd', 2, 0x13c6), Register('xmm14_bg', 1, 0x13c6), Register('xmm14_bh', 1, 0x13c7), Register('xmm14_qb', 8, 0x13c8), Register('xmm14_dc', 4, 0x13c8), Register('xmm14_we', 2, 0x13c8), Register('xmm14_bi', 1, 0x13c8), Register('xmm14_bj', 1, 0x13c9), Register('xmm14_wf', 2, 0x13ca), Register('xmm14_bk', 1, 0x13ca), Register('xmm14_bl', 1, 0x13cb), Register('xmm14_dd', 4, 0x13cc), Register('xmm14_wg', 2, 0x13cc), Register('xmm14_bm', 1, 0x13cc), Register('xmm14_bn', 1, 0x13cd), Register('xmm14_wh', 2, 0x13ce), Register('xmm14_bo', 1, 0x13ce), Register('xmm14_bp', 1, 0x13cf), Register('ymm14_h', 16, 0x13d0), Register('ymm15', 32, 0x13e0), Register('xmm15', 16, 0x13e0), Register('xmm15_qa', 8, 0x13e0), Register('xmm15_da', 4, 0x13e0), Register('xmm15_wa', 2, 0x13e0), Register('xmm15_ba', 1, 0x13e0), Register('xmm15_bb', 1, 0x13e1), Register('xmm15_wb', 2, 0x13e2), Register('xmm15_bc', 1, 0x13e2), Register('xmm15_bd', 1, 0x13e3), Register('xmm15_db', 4, 0x13e4), Register('xmm15_wc', 2, 0x13e4), Register('xmm15_be', 1, 0x13e4), Register('xmm15_bf', 1, 0x13e5), Register('xmm15_wd', 2, 0x13e6), Register('xmm15_bg', 1, 0x13e6), Register('xmm15_bh', 1, 0x13e7), Register('xmm15_qb', 8, 0x13e8), Register('xmm15_dc', 4, 0x13e8), Register('xmm15_we', 2, 0x13e8), Register('xmm15_bi', 1, 0x13e8), Register('xmm15_bj', 1, 0x13e9), Register('xmm15_wf', 2, 0x13ea), Register('xmm15_bk', 1, 0x13ea), Register('xmm15_bl', 1, 0x13eb), Register('xmm15_dd', 4, 0x13ec), Register('xmm15_wg', 2, 0x13ec), Register('xmm15_bm', 1, 0x13ec), Register('xmm15_bn', 1, 0x13ed), Register('xmm15_wh', 2, 0x13ee), Register('xmm15_bo', 1, 0x13ee), Register('xmm15_bp', 1, 0x13ef), Register('ymm15_h', 16, 0x13f0), Register('xmmtmp1', 16, 0x1400), Register('xmmtmp1_qa', 8, 0x1400), Register('xmmtmp1_da', 4, 0x1400), Register('xmmtmp1_db', 4, 0x1404), Register('xmmtmp1_qb', 8, 0x1408), Register('xmmtmp1_dc', 4, 0x1408), Register('xmmtmp1_dd', 4, 0x140c), Register('xmmtmp2', 16, 0x1410), Register('xmmtmp2_qa', 8, 0x1410), Register('xmmtmp2_da', 4, 0x1410), Register('xmmtmp2_db', 4, 0x1414), Register('xmmtmp2_qb', 8, 0x1418), Register('xmmtmp2_dc', 4, 0x1418), Register('xmmtmp2_dd', 4, 0x141c), Register('contextreg', 4, 0x2000), Register('idtr', 6, 0x2200), Register('idtr_limit', 2, 0x2200), Register('idtr_address', 4, 0x2202), Register('gdtr', 6, 0x2210), Register('gdtr_limit', 2, 0x2210), Register('gdtr_address', 4, 0x2212), Register('ldtr', 6, 0x2220), Register('ldtr_limit', 2, 0x2220), Register('ldtr_address', 4, 0x2222), Register('tr', 6, 0x2230), Register('tr_limit', 2, 0x2230), Register('tr_address', 4, 0x2232) ]
class ArchPcode_avr8_LE_16_extended(ArchPcode): name = 'avr8:LE:16:extended' pcode_arch = 'avr8:LE:16:extended' description = 'AVR8 with 22-bit word addressable code space' bits = 16 ip_offset = 0x42 sp_offset = 0x3d bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('sp', 2, 0x3d), Register('spl', 1, 0x3d), Register('sph', 1, 0x3e), Register('pc', 2, 0x42, alias_names=('ip', )), Register('cflg', 1, 0x80), Register('zflg', 1, 0x81), Register('nflg', 1, 0x82), Register('vflg', 1, 0x83), Register('sflg', 1, 0x84), Register('hflg', 1, 0x85), Register('tflg', 1, 0x86), Register('iflg', 1, 0x87), Register('skip', 1, 0x88), Register('contextreg', 4, 0x90), Register('r1r0', 2, 0x0), Register('r0', 1, 0x0), Register('r1', 1, 0x1), Register('r3r2', 2, 0x2), Register('r2', 1, 0x2), Register('r3', 1, 0x3), Register('r5r4', 2, 0x4), Register('r4', 1, 0x4), Register('r5', 1, 0x5), Register('r7r6', 2, 0x6), Register('r6', 1, 0x6), Register('r7', 1, 0x7), Register('r9r8', 2, 0x8), Register('r8', 1, 0x8), Register('r9', 1, 0x9), Register('r11r10', 2, 0xa), Register('r10', 1, 0xa), Register('r11', 1, 0xb), Register('r13r12', 2, 0xc), Register('r12', 1, 0xc), Register('r13', 1, 0xd), Register('r15r14', 2, 0xe), Register('r14', 1, 0xe), Register('r15', 1, 0xf), Register('r19r18r17r16', 4, 0x10), Register('r17r16', 2, 0x10), Register('r16', 1, 0x10), Register('r17', 1, 0x11), Register('r19r18', 2, 0x12), Register('r18', 1, 0x12), Register('r19', 1, 0x13), Register('r23r22r21r20', 4, 0x14), Register('r21r20', 2, 0x14), Register('r20', 1, 0x14), Register('r21', 1, 0x15), Register('r23r22', 2, 0x16), Register('r22', 1, 0x16), Register('r23', 1, 0x17), Register('w', 2, 0x18), Register('wlo', 1, 0x18), Register('whi', 1, 0x19), Register('x', 2, 0x1a), Register('xlo', 1, 0x1a), Register('xhi', 1, 0x1b), Register('y', 2, 0x1c), Register('ylo', 1, 0x1c), Register('yhi', 1, 0x1d), Register('z', 2, 0x1e), Register('zlo', 1, 0x1e), Register('zhi', 1, 0x1f), Register('rampd', 1, 0x58), Register('rampx', 1, 0x59), Register('rampy', 1, 0x5a), Register('rampz', 1, 0x5b), Register('eind', 1, 0x5c), Register('sreg', 1, 0x5f) ]
class ArchPcode_6502_LE_16_default(ArchPcode): name = '6502:LE:16:default' pcode_arch = '6502:LE:16:default' description = '6502 Microcontroller Family' bits = 16 ip_offset = 0x20 sp_offset = 0x22 bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('a', 1, 0x0), Register('x', 1, 0x1), Register('y', 1, 0x2), Register('p', 1, 0x3), Register('pc', 2, 0x20, alias_names=('ip',)), Register('pcl', 1, 0x20), Register('pch', 1, 0x21), Register('sp', 2, 0x22), Register('s', 1, 0x22), Register('sh', 1, 0x23), Register('n', 1, 0x30), Register('v', 1, 0x31), Register('b', 1, 0x32), Register('d', 1, 0x33), Register('i', 1, 0x34), Register('z', 1, 0x35), Register('c', 1, 0x36) ]
class ArchPcode_HC08_BE_16_default(ArchPcode): name = 'HC08:BE:16:default' pcode_arch = 'HC08:BE:16:default' description = 'HC08 Microcontroller Family' bits = 16 ip_offset = 0x20 sp_offset = 0x22 bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('a', 1, 0x0), Register('hix', 2, 0x10), Register('hi', 1, 0x10), Register('x', 1, 0x11), Register('pc', 2, 0x20, alias_names=('ip',)), Register('pch', 1, 0x20), Register('pcl', 1, 0x21), Register('sp', 2, 0x22), Register('sph', 1, 0x22), Register('spl', 1, 0x23), Register('ccr', 1, 0x30) ]
class ArchPcode_ARM_LE_32_v8T(ArchPcode): name = 'ARM:LE:32:v8T' pcode_arch = 'ARM:LE:32:v8T' description = 'Generic ARM/Thumb v8 little endian (Thumb is default)' bits = 32 ip_offset = 0x5c sp_offset = 0x54 bp_offset = sp_offset instruction_endness = Endness.LE register_list = [ Register('contextreg', 8, 0x0), Register('r0', 4, 0x20), Register('r1', 4, 0x24), Register('r2', 4, 0x28), Register('r3', 4, 0x2c), Register('r4', 4, 0x30), Register('r5', 4, 0x34), Register('r6', 4, 0x38), Register('r7', 4, 0x3c), Register('r8', 4, 0x40), Register('r9', 4, 0x44), Register('r10', 4, 0x48), Register('r11', 4, 0x4c), Register('r12', 4, 0x50), Register('sp', 4, 0x54), Register('lr', 4, 0x58), Register('pc', 4, 0x5c, alias_names=('ip', )), Register('ng', 1, 0x60), Register('zr', 1, 0x61), Register('cy', 1, 0x62), Register('ov', 1, 0x63), Register('tmpng', 1, 0x64), Register('tmpzr', 1, 0x65), Register('tmpcy', 1, 0x66), Register('tmpov', 1, 0x67), Register('shift_carry', 1, 0x68), Register('tb', 1, 0x69), Register('q', 1, 0x6a), Register('ge1', 1, 0x6b), Register('ge2', 1, 0x6c), Register('ge3', 1, 0x6d), Register('ge4', 1, 0x6e), Register('cpsr', 4, 0x70), Register('spsr', 4, 0x74), Register('mult_addr', 4, 0x80), Register('r14_svc', 4, 0x84), Register('r13_svc', 4, 0x88), Register('spsr_svc', 4, 0x8c), Register('mult_dat16', 16, 0x90), Register('mult_dat8', 8, 0x90), Register('fpsr', 4, 0xa0), Register('fpsid', 4, 0xb0), Register('isamodeswitch', 1, 0xb0), Register('fpscr', 4, 0xb4), Register('fpexc', 4, 0xb8), Register('mvfr0', 4, 0xbc), Register('mvfr1', 4, 0xc0), Register('fp0', 10, 0x100), Register('fp1', 10, 0x10a), Register('fp2', 10, 0x114), Register('fp3', 10, 0x11e), Register('fp4', 10, 0x128), Register('fp5', 10, 0x132), Register('fp6', 10, 0x13c), Register('fp7', 10, 0x146), Register('cr0', 4, 0x200), Register('cr1', 4, 0x204), Register('cr2', 4, 0x208), Register('cr3', 4, 0x20c), Register('cr4', 4, 0x210), Register('cr5', 4, 0x214), Register('cr6', 4, 0x218), Register('cr7', 4, 0x21c), Register('cr8', 4, 0x220), Register('cr9', 4, 0x224), Register('cr10', 4, 0x228), Register('cr11', 4, 0x22c), Register('cr12', 4, 0x230), Register('cr13', 4, 0x234), Register('cr14', 4, 0x238), Register('cr15', 4, 0x23c), Register('q0', 16, 0x300), Register('d0', 8, 0x300), Register('s0', 4, 0x300), Register('s1', 4, 0x304), Register('d1', 8, 0x308), Register('s2', 4, 0x308), Register('s3', 4, 0x30c), Register('q1', 16, 0x310), Register('d2', 8, 0x310), Register('s4', 4, 0x310), Register('s5', 4, 0x314), Register('d3', 8, 0x318), Register('s6', 4, 0x318), Register('s7', 4, 0x31c), Register('q2', 16, 0x320), Register('d4', 8, 0x320), Register('s8', 4, 0x320), Register('s9', 4, 0x324), Register('d5', 8, 0x328), Register('s10', 4, 0x328), Register('s11', 4, 0x32c), Register('q3', 16, 0x330), Register('d6', 8, 0x330), Register('s12', 4, 0x330), Register('s13', 4, 0x334), Register('d7', 8, 0x338), Register('s14', 4, 0x338), Register('s15', 4, 0x33c), Register('q4', 16, 0x340), Register('d8', 8, 0x340), Register('s16', 4, 0x340), Register('s17', 4, 0x344), Register('d9', 8, 0x348), Register('s18', 4, 0x348), Register('s19', 4, 0x34c), Register('q5', 16, 0x350), Register('d10', 8, 0x350), Register('s20', 4, 0x350), Register('s21', 4, 0x354), Register('d11', 8, 0x358), Register('s22', 4, 0x358), Register('s23', 4, 0x35c), Register('q6', 16, 0x360), Register('d12', 8, 0x360), Register('s24', 4, 0x360), Register('s25', 4, 0x364), Register('d13', 8, 0x368), Register('s26', 4, 0x368), Register('s27', 4, 0x36c), Register('q7', 16, 0x370), Register('d14', 8, 0x370), Register('s28', 4, 0x370), Register('s29', 4, 0x374), Register('d15', 8, 0x378), Register('s30', 4, 0x378), Register('s31', 4, 0x37c), Register('q8', 16, 0x380), Register('d16', 8, 0x380), Register('d17', 8, 0x388), Register('q9', 16, 0x390), Register('d18', 8, 0x390), Register('d19', 8, 0x398), Register('q10', 16, 0x3a0), Register('d20', 8, 0x3a0), Register('d21', 8, 0x3a8), Register('q11', 16, 0x3b0), Register('d22', 8, 0x3b0), Register('d23', 8, 0x3b8), Register('q12', 16, 0x3c0), Register('d24', 8, 0x3c0), Register('d25', 8, 0x3c8), Register('q13', 16, 0x3d0), Register('d26', 8, 0x3d0), Register('d27', 8, 0x3d8), Register('q14', 16, 0x3e0), Register('d28', 8, 0x3e0), Register('d29', 8, 0x3e8), Register('q15', 16, 0x3f0), Register('d30', 8, 0x3f0), Register('d31', 8, 0x3f8) ]
class ArchPcode_MIPS_BE_64_64_32addr(ArchPcode): name = 'MIPS:BE:64:64-32addr' pcode_arch = 'MIPS:BE:64:64-32addr' description = 'MIPS64 32-bit addresses, big endian, with mips16e' bits = 32 ip_offset = 0x100 sp_offset = 0xe8 bp_offset = sp_offset instruction_endness = Endness.BE register_list = [ Register('zero', 8, 0x0), Register('zero_hi', 4, 0x0), Register('zero_lo', 4, 0x4), Register('at', 8, 0x8), Register('at_hi', 4, 0x8), Register('at_lo', 4, 0xc), Register('v0', 8, 0x10), Register('v0_hi', 4, 0x10), Register('v0_lo', 4, 0x14), Register('v1', 8, 0x18), Register('v1_hi', 4, 0x18), Register('v1_lo', 4, 0x1c), Register('a0', 8, 0x20), Register('a0_hi', 4, 0x20), Register('a0_lo', 4, 0x24), Register('a1', 8, 0x28), Register('a1_hi', 4, 0x28), Register('a1_lo', 4, 0x2c), Register('a2', 8, 0x30), Register('a2_hi', 4, 0x30), Register('a2_lo', 4, 0x34), Register('a3', 8, 0x38), Register('a3_hi', 4, 0x38), Register('a3_lo', 4, 0x3c), Register('t0', 8, 0x40), Register('t0_hi', 4, 0x40), Register('t0_lo', 4, 0x44), Register('t1', 8, 0x48), Register('t1_hi', 4, 0x48), Register('t1_lo', 4, 0x4c), Register('t2', 8, 0x50), Register('t2_hi', 4, 0x50), Register('t2_lo', 4, 0x54), Register('t3', 8, 0x58), Register('t3_hi', 4, 0x58), Register('t3_lo', 4, 0x5c), Register('t4', 8, 0x60), Register('t4_hi', 4, 0x60), Register('t4_lo', 4, 0x64), Register('t5', 8, 0x68), Register('t5_hi', 4, 0x68), Register('t5_lo', 4, 0x6c), Register('t6', 8, 0x70), Register('t6_hi', 4, 0x70), Register('t6_lo', 4, 0x74), Register('t7', 8, 0x78), Register('t7_hi', 4, 0x78), Register('t7_lo', 4, 0x7c), Register('s0', 8, 0x80), Register('s0_hi', 4, 0x80), Register('s0_lo', 4, 0x84), Register('s1', 8, 0x88), Register('s1_hi', 4, 0x88), Register('s1_lo', 4, 0x8c), Register('s2', 8, 0x90), Register('s2_hi', 4, 0x90), Register('s2_lo', 4, 0x94), Register('s3', 8, 0x98), Register('s3_hi', 4, 0x98), Register('s3_lo', 4, 0x9c), Register('s4', 8, 0xa0), Register('s4_hi', 4, 0xa0), Register('s4_lo', 4, 0xa4), Register('s5', 8, 0xa8), Register('s5_hi', 4, 0xa8), Register('s5_lo', 4, 0xac), Register('s6', 8, 0xb0), Register('s6_hi', 4, 0xb0), Register('s6_lo', 4, 0xb4), Register('s7', 8, 0xb8), Register('s7_hi', 4, 0xb8), Register('s7_lo', 4, 0xbc), Register('t8', 8, 0xc0), Register('t8_hi', 4, 0xc0), Register('t8_lo', 4, 0xc4), Register('t9', 8, 0xc8), Register('t9_hi', 4, 0xc8), Register('t9_lo', 4, 0xcc), Register('k0', 8, 0xd0), Register('k0_hi', 4, 0xd0), Register('k0_lo', 4, 0xd4), Register('k1', 8, 0xd8), Register('k1_hi', 4, 0xd8), Register('k1_lo', 4, 0xdc), Register('gp', 8, 0xe0), Register('gp_hi', 4, 0xe0), Register('gp_lo', 4, 0xe4), Register('sp', 8, 0xe8), Register('sp_hi', 4, 0xe8), Register('sp_lo', 4, 0xec), Register('s8', 8, 0xf0), Register('s8_hi', 4, 0xf0), Register('s8_lo', 4, 0xf4), Register('ra', 8, 0xf8), Register('ra_hi', 4, 0xf8), Register('ra_lo', 4, 0xfc), Register('pc', 8, 0x100, alias_names=('ip', )), Register('pc_hi', 4, 0x100), Register('pc_lo', 4, 0x104), Register('f0', 8, 0x1000), Register('f1', 8, 0x1008), Register('f2', 8, 0x1010), Register('f3', 8, 0x1018), Register('f4', 8, 0x1020), Register('f5', 8, 0x1028), Register('f6', 8, 0x1030), Register('f7', 8, 0x1038), Register('f8', 8, 0x1040), Register('f9', 8, 0x1048), Register('f10', 8, 0x1050), Register('f11', 8, 0x1058), Register('f12', 8, 0x1060), Register('f13', 8, 0x1068), Register('f14', 8, 0x1070), Register('f15', 8, 0x1078), Register('f16', 8, 0x1080), Register('f17', 8, 0x1088), Register('f18', 8, 0x1090), Register('f19', 8, 0x1098), Register('f20', 8, 0x10a0), Register('f21', 8, 0x10a8), Register('f22', 8, 0x10b0), Register('f23', 8, 0x10b8), Register('f24', 8, 0x10c0), Register('f25', 8, 0x10c8), Register('f26', 8, 0x10d0), Register('f27', 8, 0x10d8), Register('f28', 8, 0x10e0), Register('f29', 8, 0x10e8), Register('f30', 8, 0x10f0), Register('f31', 8, 0x10f8), Register('fir', 4, 0x1200), Register('fccr', 4, 0x1204), Register('fexr', 4, 0x1208), Register('fenr', 4, 0x120c), Register('fcsr', 4, 0x1210), Register('index', 8, 0x2000), Register('random', 8, 0x2008), Register('entrylo0', 8, 0x2010), Register('entrylo1', 8, 0x2018), Register('context', 8, 0x2020), Register('pagemask', 8, 0x2028), Register('wired', 8, 0x2030), Register('hwrena', 8, 0x2038), Register('badvaddr', 8, 0x2040), Register('count', 8, 0x2048), Register('entryhi', 8, 0x2050), Register('compare', 8, 0x2058), Register('status', 8, 0x2060), Register('cause', 8, 0x2068), Register('epc', 8, 0x2070), Register('prid', 8, 0x2078), Register('config', 8, 0x2080), Register('lladdr', 8, 0x2088), Register('watchlo', 8, 0x2090), Register('watchhi', 8, 0x2098), Register('xcontext', 8, 0x20a0), Register('cop0_reg21', 8, 0x20a8), Register('cop0_reg22', 8, 0x20b0), Register('debug', 8, 0x20b8), Register('depc', 8, 0x20c0), Register('perfcnt', 8, 0x20c8), Register('errctl', 8, 0x20d0), Register('cacheerr', 8, 0x20d8), Register('taglo', 8, 0x20e0), Register('taghi', 8, 0x20e8), Register('errorepc', 8, 0x20f0), Register('desave', 8, 0x20f8), Register('mvpcontrol', 8, 0x2100), Register('vpecontrol', 8, 0x2108), Register('tcstatus', 8, 0x2110), Register('cop0_reg3.1', 8, 0x2118), Register('contextconfig', 8, 0x2120), Register('pagegrain', 8, 0x2128), Register('srsconf0', 8, 0x2130), Register('cop0_reg7.1', 8, 0x2138), Register('cop0_reg8.1', 8, 0x2140), Register('cop0_reg9.1', 8, 0x2148), Register('cop0_reg10.1', 8, 0x2150), Register('cop0_reg11.1', 8, 0x2158), Register('intctl', 8, 0x2160), Register('cop0_reg13.1', 8, 0x2168), Register('cop0_reg14.1', 8, 0x2170), Register('ebase', 8, 0x2178), Register('config1', 8, 0x2180), Register('cop0_reg17.1', 8, 0x2188), Register('watchlo.1', 8, 0x2190), Register('watchhi.1', 8, 0x2198), Register('cop0_reg20.1', 8, 0x21a0), Register('cop0_reg21.1', 8, 0x21a8), Register('cop0_reg22.1', 8, 0x21b0), Register('tracecontrol', 8, 0x21b8), Register('cop0_reg24.1', 8, 0x21c0), Register('perfcnt.1', 8, 0x21c8), Register('cop0_reg26.1', 8, 0x21d0), Register('cacheerr.1', 8, 0x21d8), Register('datalo.1', 8, 0x21e0), Register('datahi.1', 8, 0x21e8), Register('cop0_reg30.1', 8, 0x21f0), Register('cop0_reg31.1', 8, 0x21f8), Register('mvpconf0', 8, 0x2200), Register('vpeconf0', 8, 0x2208), Register('tcbind', 8, 0x2210), Register('cop0_reg3.2', 8, 0x2218), Register('cop0_reg4.2', 8, 0x2220), Register('cop0_reg5.2', 8, 0x2228), Register('srsconf1', 8, 0x2230), Register('cop0_reg7.2', 8, 0x2238), Register('cop0_reg8.2', 8, 0x2240), Register('cop0_reg9.2', 8, 0x2248), Register('cop0_reg10.2', 8, 0x2250), Register('cop0_reg11.2', 8, 0x2258), Register('srsctl', 8, 0x2260), Register('cop0_reg13.2', 8, 0x2268), Register('cop0_reg14.2', 8, 0x2270), Register('cop0_reg15.2', 8, 0x2278), Register('config2', 8, 0x2280), Register('cop0_reg17.2', 8, 0x2288), Register('watchlo.2', 8, 0x2290), Register('watchhi.2', 8, 0x2298), Register('cop0_reg20.2', 8, 0x22a0), Register('cop0_reg21.2', 8, 0x22a8), Register('cop0_reg22.2', 8, 0x22b0), Register('tracecontrol2', 8, 0x22b8), Register('cop0_reg24.2', 8, 0x22c0), Register('perfcnt.2', 8, 0x22c8), Register('cop0_reg26.2', 8, 0x22d0), Register('cacheerr.2', 8, 0x22d8), Register('taglo.2', 8, 0x22e0), Register('taghi.2', 8, 0x22e8), Register('cop0_reg30.2', 8, 0x22f0), Register('cop0_reg31.2', 8, 0x22f8), Register('mvpconf1', 8, 0x2300), Register('vpeconf1', 8, 0x2308), Register('tcrestart', 8, 0x2310), Register('cop0_reg3.3', 8, 0x2318), Register('cop0_reg4.3', 8, 0x2320), Register('cop0_reg5.3', 8, 0x2328), Register('srsconf2', 8, 0x2330), Register('cop0_reg7.3', 8, 0x2338), Register('cop0_reg8.3', 8, 0x2340), Register('cop0_reg9.3', 8, 0x2348), Register('cop0_reg10.3', 8, 0x2350), Register('cop0_reg11.3', 8, 0x2358), Register('srsmap', 8, 0x2360), Register('cop0_reg13.3', 8, 0x2368), Register('cop0_reg14.3', 8, 0x2370), Register('cop0_reg15.3', 8, 0x2378), Register('config3', 8, 0x2380), Register('cop0_reg17.3', 8, 0x2388), Register('watchlo.3', 8, 0x2390), Register('watchhi.3', 8, 0x2398), Register('cop0_reg20.3', 8, 0x23a0), Register('cop0_reg21.3', 8, 0x23a8), Register('cop0_reg22.3', 8, 0x23b0), Register('usertracedata', 8, 0x23b8), Register('cop0_reg24.3', 8, 0x23c0), Register('perfcnt.3', 8, 0x23c8), Register('cop0_reg26.3', 8, 0x23d0), Register('cacheerr.3', 8, 0x23d8), Register('datalo.3', 8, 0x23e0), Register('datahi.3', 8, 0x23e8), Register('cop0_reg30.3', 8, 0x23f0), Register('cop0_reg31.3', 8, 0x23f8), Register('cop0_reg0.4', 8, 0x2400), Register('yqmask', 8, 0x2408), Register('tchalt', 8, 0x2410), Register('cop0_reg3.4', 8, 0x2418), Register('cop0_reg4.4', 8, 0x2420), Register('cop0_reg5.4', 8, 0x2428), Register('srsconf3', 8, 0x2430), Register('cop0_reg7.4', 8, 0x2438), Register('cop0_reg8.4', 8, 0x2440), Register('cop0_reg9.4', 8, 0x2448), Register('cop0_reg10.4', 8, 0x2450), Register('cop0_reg11.4', 8, 0x2458), Register('cop0_reg12.4', 8, 0x2460), Register('cop0_reg13.4', 8, 0x2468), Register('cop0_reg14.4', 8, 0x2470), Register('cop0_reg15.4', 8, 0x2478), Register('cop0_reg16.4', 8, 0x2480), Register('cop0_reg17.4', 8, 0x2488), Register('watchlo.4', 8, 0x2490), Register('watchhi.4', 8, 0x2498), Register('cop0_reg20.4', 8, 0x24a0), Register('cop0_reg21.4', 8, 0x24a8), Register('cop0_reg22.4', 8, 0x24b0), Register('tracebpc', 8, 0x24b8), Register('cop0_reg24.4', 8, 0x24c0), Register('perfcnt.4', 8, 0x24c8), Register('cop0_reg26.4', 8, 0x24d0), Register('cacheerr.4', 8, 0x24d8), Register('taglo.4', 8, 0x24e0), Register('taghi.4', 8, 0x24e8), Register('cop0_reg30.4', 8, 0x24f0), Register('cop0_reg31.4', 8, 0x24f8), Register('cop0_reg0.5', 8, 0x2500), Register('vpeschedule', 8, 0x2508), Register('tccontext', 8, 0x2510), Register('cop0_reg3.5', 8, 0x2518), Register('cop0_reg4.5', 8, 0x2520), Register('cop0_reg5.5', 8, 0x2528), Register('srsconf4', 8, 0x2530), Register('cop0_reg7.5', 8, 0x2538), Register('cop0_reg8.5', 8, 0x2540), Register('cop0_reg9.5', 8, 0x2548), Register('cop0_reg10.5', 8, 0x2550), Register('cop0_reg11.5', 8, 0x2558), Register('cop0_reg12.5', 8, 0x2560), Register('cop0_reg13.5', 8, 0x2568), Register('cop0_reg14.5', 8, 0x2570), Register('cop0_reg15.5', 8, 0x2578), Register('cop0_reg16.5', 8, 0x2580), Register('cop0_reg17.5', 8, 0x2588), Register('watchlo.5', 8, 0x2590), Register('watchhi.5', 8, 0x2598), Register('cop0_reg20.5', 8, 0x25a0), Register('cop0_reg21.5', 8, 0x25a8), Register('cop0_reg22.5', 8, 0x25b0), Register('cop0_reg23.5', 8, 0x25b8), Register('cop0_reg24.5', 8, 0x25c0), Register('perfcnt.5', 8, 0x25c8), Register('cop0_reg26.5', 8, 0x25d0), Register('cacheerr.5', 8, 0x25d8), Register('datalo.5', 8, 0x25e0), Register('datahi.5', 8, 0x25e8), Register('cop0_reg30.5', 8, 0x25f0), Register('cop0_reg31.5', 8, 0x25f8), Register('cop0_reg0.6', 8, 0x2600), Register('vpeschefback', 8, 0x2608), Register('tcschedule', 8, 0x2610), Register('cop0_reg3.6', 8, 0x2618), Register('cop0_reg4.6', 8, 0x2620), Register('cop0_reg5.6', 8, 0x2628), Register('cop0_reg6.6', 8, 0x2630), Register('cop0_reg7.6', 8, 0x2638), Register('cop0_reg8.6', 8, 0x2640), Register('cop0_reg9.6', 8, 0x2648), Register('cop0_reg10.6', 8, 0x2650), Register('cop0_reg11.6', 8, 0x2658), Register('cop0_reg12.6', 8, 0x2660), Register('cop0_reg13.6', 8, 0x2668), Register('cop0_reg14.6', 8, 0x2670), Register('cop0_reg15.6', 8, 0x2678), Register('cop0_reg16.6', 8, 0x2680), Register('cop0_reg17.6', 8, 0x2688), Register('watchlo.6', 8, 0x2690), Register('watchhi.6', 8, 0x2698), Register('cop0_reg20.6', 8, 0x26a0), Register('cop0_reg21.6', 8, 0x26a8), Register('cop0_reg22.6', 8, 0x26b0), Register('cop0_reg23.6', 8, 0x26b8), Register('cop0_reg24.6', 8, 0x26c0), Register('perfcnt.6', 8, 0x26c8), Register('cop0_reg26.6', 8, 0x26d0), Register('cacheerr.6', 8, 0x26d8), Register('taglo.6', 8, 0x26e0), Register('taghi.6', 8, 0x26e8), Register('cop0_reg30.6', 8, 0x26f0), Register('cop0_reg31.6', 8, 0x26f8), Register('cop0_reg0.7', 8, 0x2700), Register('vpeopt', 8, 0x2708), Register('tcschefback', 8, 0x2710), Register('cop0_reg3.7', 8, 0x2718), Register('cop0_reg4.7', 8, 0x2720), Register('cop0_reg5.7', 8, 0x2728), Register('cop0_reg6.7', 8, 0x2730), Register('cop0_reg7.7', 8, 0x2738), Register('cop0_reg8.7', 8, 0x2740), Register('cop0_reg9.7', 8, 0x2748), Register('cop0_reg10.7', 8, 0x2750), Register('cop0_reg11.7', 8, 0x2758), Register('cop0_reg12.7', 8, 0x2760), Register('cop0_reg13.7', 8, 0x2768), Register('cop0_reg14.7', 8, 0x2770), Register('cop0_reg15.7', 8, 0x2778), Register('cop0_reg16.7', 8, 0x2780), Register('cop0_reg17.7', 8, 0x2788), Register('watchlo.7', 8, 0x2790), Register('watchhi.7', 8, 0x2798), Register('cop0_reg20.7', 8, 0x27a0), Register('cop0_reg21.7', 8, 0x27a8), Register('cop0_reg22.7', 8, 0x27b0), Register('cop0_reg23.7', 8, 0x27b8), Register('cop0_reg24.7', 8, 0x27c0), Register('perfcnt.7', 8, 0x27c8), Register('cop0_reg26.7', 8, 0x27d0), Register('cacheerr.7', 8, 0x27d8), Register('datalo.7', 8, 0x27e0), Register('datahi.7', 8, 0x27e8), Register('cop0_reg30.7', 8, 0x27f0), Register('cop0_reg31.7', 8, 0x27f8), Register('hi', 8, 0x3000), Register('lo', 8, 0x3008), Register('hi1', 8, 0x3010), Register('lo1', 8, 0x3018), Register('hi2', 8, 0x3020), Register('lo2', 8, 0x3028), Register('hi3', 8, 0x3030), Register('lo3', 8, 0x3038), Register('tsp', 8, 0x3040), Register('isamodeswitch', 1, 0x3f00), Register('contextreg', 4, 0x4000) ]