def leds(prefix, led_gnd, led_pwr, pwm, nSHDN, temp_gnd, temp_pwr, temp_bus):
# maximum current
# driver: > 1 A/channel
# LED: 1 A DC, 5 A pulses
ref = Net(prefix+'ref') # 1.05 V
yield capacitor(0.1e-6)(prefix+'C1', A=ref, B=led_gnd)
refdiv = Net(prefix+'refdiv') # 1.00 V
yield resistor(4.99e3)(prefix+'R1', A=ref, B=refdiv)
yield resistor(100e3)(prefix+'R2', A=refdiv, B=led_gnd)
assert len(pwm) == 4
cap = [Net(prefix+'cap%i' % (i,)) for i in xrange(4)]
led = [Net(prefix+'led%i' % (i,)) for i in xrange(4)]
cat = [Net(prefix+'cat%i' % (i,)) for i in xrange(4)]
sw = [Net(prefix+'sw%i' % (i,)) for i in xrange(4)]
vadj = [refdiv for i in xrange(4)]
vc = [Net(prefix+'vc%i' % (i,)) for i in xrange(4)]
yield resistor(10e3)(prefix+'R3', A=nSHDN, B=led_gnd)
for i in xrange(4):
yield trace_jumper(5*MIL)(prefix+'D%iJ' % (i,), A=led_pwr, B=cap[i])
yield resistor(100e-3)(prefix+'D%iR' % (i,), A=cap[i], B=led[i]) # refdiv setting & this = 1.00 A thru LED # XXX check power rating
yield VSMY7850X01(prefix+'D%i' % (i,),
A=led[i],
C=cat[i],
)
yield _capacitor.capacitor(0.22e-6, voltage=20, packages=frozenset(['0805 ']))(prefix+'D%iC' % (i,), A=led_pwr, B=cat[i])
yield inductor.inductor(Interval.from_center_and_relative_error(10e-6, 0.3), minimum_current=1, maximum_resistance=100e-3)(prefix+'D%iL' % (i,), A=cat[i], B=sw[i])
yield DFLS140L_7(prefix+'D%iD' % (i+4,), A=sw[i], C=led_pwr)
yield capacitor(1e-9, voltage=20)(prefix+'D%iC2' % (i,), A=vc[i], B=led_gnd)
yield _capacitor.capacitor(2.2e-6, voltage=20, packages=frozenset(['0805 ']))(prefix+'D%iC_BYP' % (i,), A=led_pwr, B=led_gnd)
yield DS18B20.DS18B20U_('D%iU' % (i,),
GND=temp_gnd,
VDD=temp_pwr,
DQ=temp_bus,
NC=led[i], # thermal connection
)
rt = Net(prefix+'rt')
yield resistor(21e3)(prefix+'RT', A=rt, B=led_gnd) # 1 MHz
yield _capacitor.capacitor(2.2e-6, voltage=20, packages=frozenset(['0805 ']))(prefix+'U3C', A=led_pwr, B=led_gnd)
yield LT3476(prefix+'U3',
GND=led_gnd,
NC=led_gnd, # better heat dissipation
VIN=led_pwr,
nSHDN=nSHDN,
REF=ref,
RT=rt,
**util.union_dicts(
{'PWM%i' % (i+1,): pwm[i] for i in xrange(4)},
{'SW%i' % (i+1,): sw[i] for i in xrange(4)},
{'CAP%i' % (i+1,): cap[i] for i in xrange(4)},
{'LED%i' % (i+1,): led[i] for i in xrange(4)},
{'VADJ%i' % (i+1,): vadj[i] for i in xrange(4)},
{'VC%i' % (i+1,): vc[i] for i in xrange(4)},
))
def camera(prefix, gnd, vcc3_3, vcc3_3_pix, vcc1_8, harness):
ibias_master = Net(prefix+'IBIAS')
yield resistor(47e3)(prefix+'R1', A=ibias_master, B=gnd) # gnd_33
vdd_18 = vcc1_8 # Net(prefix+'vdd_18')
for i in xrange(3): yield capacitor(100e-9)(prefix+'C1%i' % i, A=vdd_18, B=gnd)
for i in xrange(2): yield capacitor( 10e-6)(prefix+'C2%i' % i, A=vdd_18, B=gnd)
vdd_33 = vcc3_3 # Net(prefix+'vdd_33')
for i in xrange(4): yield capacitor(100e-9)(prefix+'C3%i' % i, A=vdd_33, B=gnd)
for i in xrange(2): yield capacitor(4.7e-6)(prefix+'C4%i' % i, A=vdd_33, B=gnd)
for i in xrange(2): yield capacitor( 10e-6)(prefix+'C5%i' % i, A=vdd_33, B=gnd)
vdd_pix = Net(prefix+'vdd_pix')
yield BLM15G.BLM15GG471SN1D(prefix+'FB1', A=vcc3_3_pix, B=vdd_pix)
for i in xrange(4): yield capacitor(4.7e-6)(prefix+'C6%i' % i, A=vdd_pix, B=gnd)
for i in xrange(2): yield _capacitor.capacitor(100e-6, voltage=3.3*1.5)(prefix+'C7%i' % i, A=vdd_pix, B=gnd) # not restricted to 0402
yield NOIV1SE1300A_QDC.NOIV1SE1300A_QDC(prefix+'U1',
vdd_33=vdd_33,
gnd_33=gnd,
vdd_pix=vdd_pix,
gnd_colpc=gnd,
vdd_18=vdd_18,
gnd_18=gnd,
mosi=harness.spi_bus.MOSI,
miso=harness.spi_bus.MISO,
sck=harness.spi_bus.SCLK,
ss_n=harness.ss_n,
clock_outn=harness.clock.N,
clock_outp=harness.clock.P,
doutn0=harness.douts[0].N,
doutp0=harness.douts[0].P,
doutn1=harness.douts[1].N,
doutp1=harness.douts[1].P,
doutn2=harness.douts[2].N,
doutp2=harness.douts[2].P,
doutn3=harness.douts[3].N,
doutp3=harness.douts[3].P,
syncn=harness.sync.N,
syncp=harness.sync.P,
lvds_clock_inn=harness.clock_in.N,
lvds_clock_inp=harness.clock_in.P,
clk_pll=gnd,
ibias_master=ibias_master,
trigger0=harness.triggers[0],
trigger1=harness.triggers[1],
trigger2=harness.triggers[2],
monitor0=harness.monitors[0],
monitor1=harness.monitors[1],
reset_n=harness.reset_n,
)
yield CMT821.CMT821(prefix+'M1')
yield resistor(100, error=0, tolerance=0.01)(prefix+'R2', A=harness.clock_in.P, B=harness.clock_in.N)
def main():
for i in xrange(4):
yield mounting_hole('M%i' % (i,))
gnd = Net('gnd')
vcc5in = Net('vcc5in') # specified at 1 A. could supply a lot more at peak if pulsed. used only for LED driver.
vcc3_3in = Net('vcc3_3in') # specification unclear; around 1 A. used only for LVDS buffers and regulators.
vcc1_2_1 = Net('vcc1_2_1') # thermal 1 (110mA)
vcc1_2_2 = Net('vcc1_2_2') # thermal 2 (110mA)
vcc1_8 = Net('vcc1_8') # CPLD (40mA)
C1_vcc1_8 = Net('C1_vcc1_8') # CMOS (75mA) - switched
C1_vcc1_8_en = Net('C1_vcc1_8_en') # XXX connect to CPLD
C2_vcc1_8 = Net('C2_vcc1_8') # CMOS (75mA) - switched
C2_vcc1_8_en = Net('C2_vcc1_8_en') # XXX connect to CPLD
vcc2_8_1 = Net('vcc2_8_1') # thermal (16mA)
vcc2_8_2 = Net('vcc2_8_2') # thermal (16mA)
vcc3_0 = Net('vcc3_0') # CPLD, thermal (4mA*2), ARM
C1_vcc3_0_main = Net('C1_vcc3_0_main') # CMOS (130mA) - switched
C1_vcc3_0_main_en = Net('C1_vcc3_0_main_en') # XXX connect to CPLD
C1_vcc3_0_pix = Net('C1_vcc3_0_pix') # CMOS (2.5mA) - switched
C1_vcc3_0_pix_en = Net('C1_vcc3_0_pix_en') # XXX connect to CPLD
C2_vcc3_0_main = Net('C2_vcc3_0_main') # CMOS (130mA) - switched
C2_vcc3_0_main_en = Net('C2_vcc3_0_main_en') # XXX connect to CPLD
C2_vcc3_0_pix = Net('C2_vcc3_0_pix') # CMOS (2.5mA) - switched
C2_vcc3_0_pix_en = Net('C2_vcc3_0_pix_en') # XXX connect to CPLD
for n, v, en in [
(vcc1_2_1 , 1.2, None),
(vcc1_2_2 , 1.2, None),
(vcc1_8 , 1.8, None),
(C1_vcc1_8 , 1.8, C1_vcc1_8_en),
(C2_vcc1_8 , 1.8, C2_vcc1_8_en),
(vcc2_8_1 , 2.8, None),
(vcc2_8_2 , 2.8, None),
(vcc3_0 , 3.0, None),
(C1_vcc3_0_main, 3.0, C1_vcc3_0_main_en),
(C1_vcc3_0_pix, 3.0, C1_vcc3_0_pix_en),
(C2_vcc3_0_main, 3.0, C2_vcc3_0_main_en),
(C2_vcc3_0_pix, 3.0, C2_vcc3_0_pix_en),
]:
if v != 1.2:
yield NCP702.by_voltage[v](n.name + 'U',
IN=vcc3_3in,
GND=gnd,
EN=vcc3_3in if en is None else en,
OUT=n,
NC=gnd, # thermal
)
yield capacitor(1e-6)(n.name + 'C1', A=vcc3_3in, B=gnd)
yield capacitor(1e-6)(n.name + 'C2', A=n, B=gnd)
else:
yield BUxxTD3WG.by_voltage[v](n.name + 'U',
VIN=vcc3_3in,
GND=gnd,
nSTBY=vcc3_3in if en is None else en,
VOUT=n,
NC=gnd, # thermal
)
yield capacitor(0.47e-6)(n.name + 'C1', A=vcc3_3in, B=gnd)
yield capacitor(0.47e-6)(n.name + 'C2', A=n, B=gnd)
shield = Net('shield')
yield _capacitor.capacitor(1e-9, voltage=250)('C2', A=shield, B=gnd)
yield resistor(1e6)('R2', A=shield, B=gnd)
pairs = {i: harnesses.LVDSPair.new('pair%i' % (i,)) for i in xrange(1, 20+1)}
yield digilent_vhdci('P1',
GND=gnd,
SHIELD=shield,
VU=vcc5in,
VCC=vcc3_3in,
CLK10_P=pairs[10].P, CLK10_N=pairs[10].N,
CLK11_P=pairs[11].P, CLK11_N=pairs[11].N,
**dict(
[('IO%i_P' % (i,), pairs[i].P) for i in range(1, 9+1)+range(12, 20+1)] +
[('IO%i_N' % (i,), pairs[i].N) for i in range(1, 9+1)+range(12, 20+1)])
)
bufout = {}
for i in [2, 3, 4, -5, -6, -10, 11, 15, 16, -17, 18, 19]:
swap = not (i < 0)
i = abs(i)
bufout[i] = harnesses.LVDSPair.new('out%i' % (i,))
a = bufout[i].swapped if swap else bufout[i]
b = pairs[i].swapped if swap else pairs[i]
yield capacitor(100e-9)('B%iC' % (i,), A=vcc3_3in, B=gnd)
yield DS10BR150TSD('B%i' % (i,),
GND=gnd,
INn=a.N,
INp=a.P,
VCC=vcc3_3in,
OUTp=b.P,
OUTn=b.N,
)
bufin = {}
for i in [-1, 20]:
swap = not (i < 0)
i = abs(i)
bufin[i] = harnesses.LVDSPair.new('out%i' % (i,))
a = pairs[i].swapped if swap else pairs[i]
b = bufin[i].swapped if swap else bufin[i]
yield capacitor(100e-9)('B%iC' % (i,), A=vcc3_3in, B=gnd)
yield DS10BR150TSD('B%i' % (i,),
GND=gnd,
INn=a.N,
INp=a.P,
VCC=vcc3_3in,
OUTp=b.P,
OUTn=b.N,
)
C1_harness = CameraHarness('C1',
clock_in=bufin[1].swapped,
douts=[bufout[6], bufout[5], bufout[4].swapped, bufout[3].swapped],
sync=bufout[2].swapped,
clock=bufout[10],
)
yield camera('C1',
gnd=gnd,
vcc1_8=C1_vcc1_8,
vcc3_3=C1_vcc3_0_main,
vcc3_3_pix=C1_vcc3_0_pix,
harness=C1_harness,
)
C2_harness = CameraHarness('C2',
clock_in=bufin[20],
douts=[bufout[15], bufout[16], bufout[17].swapped, bufout[18]],
sync=bufout[19],
clock=bufout[11],
)
yield camera('C2',
gnd=gnd,
vcc1_8=C2_vcc1_8,
vcc3_3=C2_vcc3_0_main,
vcc3_3_pix=C2_vcc3_0_pix,
harness=C2_harness,
)
lepton1 = LeptonHarness('T1',
gnd=gnd,
vddc=vcc1_2_1,
vdd=vcc2_8_1,
vddio=vcc3_0,
)
yield lepton1.make()
lepton2 = LeptonHarness('T2',
gnd=gnd,
vddc=vcc1_2_2,
vdd=vcc2_8_2,
vddio=vcc3_0,
)
yield lepton2.make()
baro_spi_bus = harnesses.SPIBus.new('baro_') # XXX connect to CPLD
baro_spi_nCS = Net('baro_spi_nCS') # XXX connect to CPLD
imu_spi_bus = harnesses.SPIBus.new('imu_') # XXX connect to CPLD
imu_spi_nCS = Net('imu_spi_nCS') # XXX connect to CPLD
imu_FSYNC = Net('imu_FSYNC') # XXX connect to CPLD
imu_INT = Net('imu_INT') # XXX connect to CPLD
yield sensors('S',
GND=gnd,
VCC=vcc3_0,
baro_spi_bus=baro_spi_bus,
baro_spi_nCS=baro_spi_nCS,
imu_spi_bus=imu_spi_bus,
imu_spi_nCS=imu_spi_nCS,
imu_FSYNC=imu_FSYNC,
imu_INT=imu_INT,
)
'''led_gnd = Net('led_gnd')
yield trace_jumper(60*MIL)('J2', A=led_gnd, B=gnd)
led_pwr = Net('led_pwr')
yield wire_terminal()('P3', T=led_pwr)
yield wire_terminal()('P4', T=led_gnd)
yield make_jumper_grid('J1', [[vcc5in, led_pwr]], grid_size=66*MIL, box_size=60*MIL)
led_pwm = [Net('led_pwm%i' % (i,)) for i in xrange(4)]
led_nSHDN = Net('led_nSHDN')
temp_bus = Net('temp_bus')
yield leds('I',
led_gnd=led_gnd,
led_pwr=vcc5in, # XXX add connector for external higher current 5V power
pwm=led_pwm,
nSHDN=led_nSHDN,
temp_gnd=gnd,
temp_pwr=vcc3_3in,
temp_bus=temp_bus,
)'''
cpld_jtag = harnesses.JTAG.new('cpld_') # XXX make connector for. make sure to use vcc3_0 for power pin
yield make_header('VREF GND TCK TDO TDI TMS'.split(' '))('P2',
VREF=vcc3_0,
GND=gnd,
TCK=cpld_jtag.TCK,
TDI=cpld_jtag.TDI,
TDO=cpld_jtag.TDO,
TMS=cpld_jtag.TMS,
)
for i in xrange(6):
yield capacitor(0.1e-6)('U2C%i' % (i,), A=vcc3_0, B=gnd)
for i in xrange(2):
yield capacitor(0.1e-6)('U2C%i' % (10+i,), A=vcc1_8, B=gnd)
yield XC2C128_6VQG100C('U2',
GND=gnd,
VCC=vcc1_8,
VAUX=vcc3_0,
TDI=cpld_jtag.TDI,
TDO=cpld_jtag.TDO,
TCK=cpld_jtag.TCK,
TMS=cpld_jtag.TMS,
# IO pins can be rearranged any which way, except that GCK pins need
# to be connected to expansion connector
VCCIO1=vcc3_0,
VCCIO2=vcc3_0,
IO1_33=pairs[7].N,
IO1_32=pairs[7].P,
IO1_30=pairs[8].N,
IO1_29=pairs[8].P,
IO1_28=pairs[9].P,
IO1_27=pairs[9].N, # GCK
IO1_24=pairs[12].N,
IO1_23=pairs[12].P, # GCK
IO1_22=pairs[13].P, # GCK
IO1_19=pairs[13].N,
IO1_18=pairs[14].P,
IO1_17=pairs[14].N,
#IO1_32=temp_bus, # XXX
#IO1_33=led_pwm[0],
#IO1_34=led_pwm[1],
#IO1_35=led_pwm[2],
#IO1_36=led_pwm[3],
#IO1_37=led_nSHDN,
IO1_39=C1_harness.spi_bus.SCLK,
IO1_40=C1_harness.spi_bus.MISO,
IO1_41=C1_harness.spi_bus.MOSI,
IO1_42=C1_harness.ss_n,
IO1_43=C1_harness.reset_n,
IO1_44=C1_harness.monitors[1],
IO1_46=C1_harness.monitors[0],
IO1_49=C1_harness.triggers[2],
IO1_50=C1_harness.triggers[1],
IO1_52=C1_harness.triggers[0],
IO1_53=lepton1.master_clk,
IO1_54=lepton1.pwr_dwn_l,
IO1_55=lepton1.reset_l,
IO1_56=lepton1.i2c_bus.SCL,
IO1_58=lepton1.i2c_bus.SDA,
IO1_59=lepton1.video_spi_bus.MOSI,
IO1_60=lepton1.video_spi_bus.MISO,
IO1_61=lepton1.video_spi_bus.SCLK,
IO1_63=lepton1.video_ss_n,
IO2_10=C2_harness.triggers[0],
IO2_9=C2_harness.triggers[1],
IO2_8=C2_harness.triggers[2],
IO2_7=C2_harness.monitors[0],
IO2_6=C2_harness.monitors[1],
IO2_4=C2_harness.reset_n,
IO2_3=C2_harness.ss_n,
IO2_2=C2_harness.spi_bus.MOSI,
IO2_1=C2_harness.spi_bus.MISO,
IO2_99=C2_harness.spi_bus.SCLK,
IO2_97=lepton2.reset_l,
IO2_96=lepton2.pwr_dwn_l,
IO2_95=lepton2.master_clk,
IO2_94=lepton2.video_ss_n,
IO2_93=lepton2.video_spi_bus.SCLK,
IO2_92=lepton2.video_spi_bus.MISO,
IO2_91=lepton2.video_spi_bus.MOSI,
IO2_90=lepton2.i2c_bus.SDA,
IO2_89=lepton2.i2c_bus.SCL,
IO1_35=C1_vcc1_8_en,
IO1_36=C1_vcc3_0_main_en,
IO1_37=C1_vcc3_0_pix_en,
IO2_13=C2_vcc3_0_pix_en,
IO2_12=C2_vcc3_0_main_en,
IO2_11=C2_vcc1_8_en,
IO2_70=baro_spi_bus.SCLK,
IO2_71=baro_spi_bus.MOSI,
IO2_72=baro_spi_bus.MISO,
IO2_73=baro_spi_nCS,
IO2_82=imu_spi_nCS,
IO2_81=imu_spi_bus.SCLK,
IO2_80=imu_spi_bus.MOSI,
IO2_79=imu_spi_bus.MISO,
IO2_78=imu_FSYNC,
IO2_77=imu_INT,
)
from autoee_components.sunex import CMT821
from autoee_components.stmicroelectronics.STM32F103TB import STM32F103TB
from autoee_components.texas_instruments.DS10BR150 import DS10BR150TSD
from autoee_components.xilinx.XC2C128 import XC2C128_6VQG100C, _XC2C128_6VQG100C_pin_names
from autoee_components.vishay_semiconductors.VSMY7850X01 import VSMY7850X01
from autoee_components.rohm_semiconductor import BUxxTD3WG
from autoee_components.linear_technology.LT3476 import LT3476
from autoee_components.murata_electronics import BLM15G
from autoee_components.measurement_specialties import MS5611_01BA03
from autoee_components.invensense import MPU_9250
from autoee_components.maxim import DS18B20
from autoee_components.diodes_incorporated.DFLS140L import DFLS140L_7
from autoee_components.header import make_header
resistor = lambda *args, **kwargs: _resistor.resistor(*args, packages=frozenset({'0402 '}), **kwargs)
capacitor = lambda *args, **kwargs: _capacitor.capacitor(*args, packages=frozenset({'0402 '}), **kwargs) # might create a problem for power filtering...
digilent_vhdci = _71430._71430_0101('''
IO1_P GND IO2_P IO3_P GND IO4_P IO5_P GND IO6_P IO7_P GND IO8_P IO9_P GND CLK10_P VCC VU
VU VCC CLK11_P GND IO12_P IO13_P GND IO14_P IO15_P GND IO16_P IO17_P GND IO18_P IO19_P GND IO20_P
IO1_N GND IO2_N IO3_N GND IO4_N IO5_N GND IO6_N IO7_N GND IO8_N IO9_N GND CLK10_N VCC VU
VU VCC CLK11_N GND IO12_N IO13_N GND IO14_N IO15_N GND IO16_N IO17_N GND IO18_N IO19_N GND IO20_N
'''.split(), 'SHIELD')
lepton = _1050281001._1050281001('''
GND GPIO3 GPIO2 GPIO1 GPIO0 GND VDDC GND
GND GND SPI_MOSI SPI_MISO SPI_CLK SPI_CS_L GND VDDIO
NC GND VDD GND SCL SDA PWR_DWN_L RESET_L
GND MASTER_CLK GND MIPI_CLK_N MIPI_CLK_P GND MIPI_DATA_N MIPI_DATA_P
'''.split())
