async def setup_and_simulate(self, prj: BagProject,
sch_params: Dict[str, Any]) -> Dict[str, Any]:
if sch_params is None:
print('loading testbench %s' % self.tb_name)
tb = prj.load_testbench(self.impl_lib, self.tb_name)
else:
print('Creating testbench %s' % self.tb_name)
tb = self._create_tb_schematic(prj, sch_params)
print('Configuring testbench %s' % self.tb_name)
tb.set_simulation_environments(self.env_list)
self.setup_testbench(tb)
for cell_name, view_name in self.sim_view_list:
tb.set_simulation_view(self.impl_lib, cell_name, view_name)
tb.update_testbench()
# run simulation and save/return raw result
print('Simulating %s' % self.tb_name)
save_dir = await tb.async_run_simulation()
print('Finished simulating %s' % self.tb_name)
results = load_sim_results(save_dir)
save_sim_results(results, self.data_fname)
return results
"""
The script for testing the Design Manager Module
This file can generate layout/schematic, Do LVS and RCX, and run overdrive test recovery testbench
To be able to use this the top level yaml file has to follow certain conventions. DTSA.yaml is an example
"""
from bag import BagProject
from bag.simulation.core import DesignManager
from bag.io import read_yaml, open_file
if __name__ == '__main__':
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
fname = 'specs_design/opamp_two_stage_1e8.yaml'
sim = DesignManager(bprj, fname)
sim.characterize_designs(generate=False,
measure=True,
load_from_file=False)
# -*- coding: utf-8 -*-
import os
from bag import BagProject
prj = BagProject()
impl_lib = 'AAATB'
dut_lib = 'demo_testbenches'
dut_cell = 'stimuli_pwl_pinmod'
fbase = os.path.join(os.environ['BAG_FRAMEWORK'], 'tutorial', 'scripts_demo')
fname_list = [
os.path.join(fbase, 'a.data'),
os.path.join(fbase, 'b.data'),
os.path.join(fbase, 'c.data')
]
sig_list = ['a', 'b', 'c']
print('create DUT module')
dsn = prj.create_design_module(dut_lib, dut_cell)
print("design DUT")
dsn.design(fname_list=fname_list, sig_list=sig_list)
print('create DUT schematic')
dsn.implement_design(impl_lib, erase=True)
# -*- coding: utf-8 -*-
import os
import matplotlib.pyplot as plt
from bag import BagProject
from bag.data import load_sim_results
prj = BagProject()
impl_lib = 'AAATB'
dut_lib = 'demo_templates'
dut_cell = 'rc_lowpass'
res = 500
cap_var = 'cload'
cap_swp_list = [100e-15, 500e-15]
tb_lib = 'demo_testbenches'
tb_cell = 'tb_tran_pwl'
fname = os.path.join(os.environ['BAG_FRAMEWORK'], 'tutorial', 'scripts_demo',
'tb_tran_pwl.data')
print('create DUT module')
dsn = prj.create_design_module(dut_lib, dut_cell)
print("design DUT")
dsn.design(res=res, cap=cap_var)
print('create DUT schematic')
dsn.implement_design(impl_lib, erase=True)
self.add_wires(layer - 1, 12, 2000, 2200, width=2, unit_mode=True),
]
nwire = len(warr_list2)
blk_w, blk_h = BiasShield.get_block_size(self.grid, layer, nwire)
result = BiasShield.connect_bias_shields(self,
layer,
warr_list2,
2 * blk_h,
lu_end_mode=1)
print(result)
if __name__ == '__main__':
with open('specs_test/abs_templates_ec/routing/bias_shield.yaml',
'r') as f:
block_specs = yaml.load(f)
local_dict = locals()
if 'bprj' not in local_dict:
print('creating BAG project')
bprj = BagProject()
else:
print('loading BAG project')
bprj = local_dict['bprj']
block_specs['impl_cell'] = 'BIAS_TEST'
block_specs['params'] = {}
bprj.generate_cell(block_specs, Test, gen_lay=True, debug=True)