def __init__(self, intf, conf):
si570_reg = {
"name":
"Si570",
"type":
"StdRegister",
"driver":
"none",
"size":
48,
"fields": [
{
"name": "RFREQ",
"size": 38,
"offset": 37
},
{
"name": "N1",
"size": 7,
"offset": 44
},
{
"name": "HS_DIV",
"size": 3,
"offset": 47
},
],
}
super(si570, self).__init__(intf, conf)
self._base_addr = conf["base_addr"]
self._reg = StdRegister(driver=None, conf=si570_reg)
self._freq = conf["init"]
def __init__(self, driver, conf):
StdRegister.__init__(self, driver, conf)
def test_gpio(self):
ID_CODE = BitLogic('0010')
BYPASS = BitLogic('1111')
DEBUG = BitLogic('1000')
ret_ir = BitLogic('0101')
# TEST REG INIT
dev1ret = StdRegister(driver=None, conf=yaml.safe_load(gpio_yaml))
dev1ret.init()
dev1ret['F1'] = 0x1
dev1ret['F2'] = 0x2f
dev1ret['F3'] = 0x2
dev1ret['F4'] = 0x17cf4
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.chip['DEV1']['F2'] = 0
self.assertFalse(dev1ret[:] == self.chip['DEV1'][:])
self.chip.set_configuration(init_yaml)
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.chip['JTAG'].reset()
# IR CODE
ret = self.chip['JTAG'].scan_ir([ID_CODE] * 2)
self.assertEqual(ret, [ret_ir] * 2)
# ID CODE
id_code = BitLogic.from_value(0x149B51C3, fmt='I')
ret = self.chip['JTAG'].scan_dr(['0' * 32] * 2)
self.assertEqual(ret, [id_code] * 2)
# BYPASS + ID CODE
bypass_code = BitLogic('0')
ret = self.chip['JTAG'].scan_ir([ID_CODE, BYPASS])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip['JTAG'].scan_dr(['0' * 32, '1'])
self.assertEqual(ret, [id_code, bypass_code])
ret = self.chip['JTAG'].scan_ir([BYPASS, ID_CODE])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip['JTAG'].scan_dr(['1', '0' * 32])
self.assertEqual(ret, [bypass_code, id_code])
# DEBUG
ret = self.chip['JTAG'].scan_ir([DEBUG, DEBUG])
self.assertEqual(ret, [ret_ir] * 2)
self.chip['JTAG'].scan_dr(['1' * 32, '0' * 1 + '1' * 30 + '0' * 1])
ret = self.chip['JTAG'].scan_dr(['0' * 32, '1' * 32])
self.assertEqual(
ret, [BitLogic('1' * 32),
BitLogic('0' * 1 + '1' * 30 + '0' * 1)])
ret = self.chip['JTAG'].scan_dr(['0' * 32, '0' * 32])
self.assertEqual(ret, [BitLogic('0' * 32), BitLogic('1' * 32)])
# SHIT IN DEV REG/DEBUG
self.chip['JTAG'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
# GPIO RETURN
dev1ret.frombytes(self.chip['GPIO_DEV1'].get_data())
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.assertFalse(dev1ret[:] == self.chip['DEV2'][:])
dev1ret.frombytes(self.chip['GPIO_DEV2'].get_data())
self.assertEqual(dev1ret[:], self.chip['DEV2'][:])
# JTAG RETURN
ret = self.chip['JTAG'].scan_dr(['0' * 32, '0' * 32])
dev1ret.set(ret[0])
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
dev1ret.set(ret[1])
self.assertEqual(dev1ret[:], self.chip['DEV2'][:])
# REPEATING REGISTER
self.chip['JTAG'].scan_dr([self.chip['DEV'][:]])
ret1 = self.chip['JTAG'].scan_dr([self.chip['DEV'][:]])
self.chip['JTAG'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
ret2 = self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
ret3 = self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
self.assertEqual(ret1[:], ret2[:])
self.assertEqual(ret2[:], ret3[:])
# REPEATING SETTING
self.chip['JTAG'].scan_dr(['1' * 32 + '0' * 32])
ret = self.chip['JTAG'].scan_dr(['0' * 32 + '0' * 32])
self.chip['DEV'].set(ret[0])
self.assertEqual(self.chip['DEV'][:], BitLogic('0' * 32 + '1' * 32))
self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
ret = self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
self.chip['DEV'].set(ret[0])
self.assertEqual(self.chip['DEV'][:],
self.chip['DEV1'][:] + self.chip['DEV2'][:])
def __init__(self, intf, conf):
super(JtagGpio, self).__init__(intf, conf)
cfg = yaml.load(self.jtag_gpio_yaml)
self.reg = StdRegister(driver=None, conf=cfg)
class JtagGpio(HardwareLayer):
'''GPIO based JTAG interface
'''
jtag_gpio_yaml = """
name : GPIO
type : StdRegister
driver : None
size : 8
fields:
- name : RESETB
size : 1
offset : 0
- name : TCK
size : 1
offset : 1
- name : TMS
size : 1
offset : 2
- name : TDI
size : 1
offset : 3
- name : TDO
size : 1
offset : 4
"""
def __init__(self, intf, conf):
super(JtagGpio, self).__init__(intf, conf)
cfg = yaml.load(self.jtag_gpio_yaml)
self.reg = StdRegister(driver=None, conf=cfg)
# self.RESETB = 0
# self.TCK = 0
# self.reg['TMS'] = 0
# self.TDI = 0
# self.TD0 = 0
def init(self):
super(JtagGpio, self).init()
def reset(self):
self.reg['RESETB'] = 0
self._write(tck=False)
self.reg['RESETB'] = 1
self._write(tck=False)
self.tms_reset()
def tms_reset(self):
for _ in range(5):
self.reg['TMS'] = 1
self._write()
self.reg['TMS'] = 0
self._write() # idle
def scan_ir(self, data):
self.reg['TMS'] = 1
self._write()
self.reg['TMS'] = 1
self._write() # select ir
return self._scan(data)
def scan_dr(self, data):
self.reg['TMS'] = 1
self._write() # select dr
return self._scan(data)
def _scan(self, data):
self.reg['TMS'] = 0
self._write() # capture
self.reg['TMS'] = 0
ret_bit = self._write(tdo=True)
ret = []
size_dev = len(data)
for dev in range(size_dev):
dev_ret = BitLogic(len(data[dev]))
size = len(data[dev])
for bit in range(size):
if dev == len(data) - 1 and bit == len(data[dev]) - 1:
self.reg['TMS'] = 1 # exit1
self.reg['TDI'] = data[dev][bit]
dev_ret[bit] = ret_bit
if bit == size - 1 and dev == size_dev - 1: # last bit
self._write()
else:
ret_bit = self._write(tdo=True)
ret.append(dev_ret)
self.reg['TDI'] = 0
self.reg['TMS'] = 1
self._write() # update
self.reg['TMS'] = 0
self._write() # idle
return ret
def _write(self, tck=True, tdo=False):
self._intf.set_data(self.reg.tobytes())
if (tck):
self.reg['TCK'] = 0
self._intf.set_data(self.reg.tobytes())
self.reg['TCK'] = 1
self._intf.set_data(self.reg.tobytes())
self.reg['TCK'] = 0
self._intf.set_data(self.reg.tobytes())
if tdo:
return (self._intf.get_data()[0] & 0b0010000) >> 4 # TODO:
def jtag_tests(self):
ID_CODE_STR = "0010"
ID_CODE = BitLogic(ID_CODE_STR)
BYPASS = BitLogic("1111")
DEBUG = BitLogic("1000")
ret_ir = BitLogic("0101")
# TEST REG INIT
dev1ret = StdRegister(driver=None, conf=yaml.safe_load(gpio_yaml))
dev1ret.init()
dev1ret["F1"] = 0x1
dev1ret["F2"] = 0x2F
dev1ret["F3"] = 0x2
dev1ret["F4"] = 0x17CF4
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
self.chip["DEV1"]["F2"] = 0
self.assertFalse(dev1ret[:] == self.chip["DEV1"][:])
self.chip.set_configuration(init_yaml)
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
self.chip["JTAG"].reset()
# IR CODE
with self.assertRaises(ValueError):
self.chip["JTAG"].scan_ir(ID_CODE_STR + ID_CODE_STR)
ret = self.chip["JTAG"].scan_ir([ID_CODE] * 2, readback=False)
self.assertEqual(ret, None)
ret = self.chip["JTAG"].scan_ir([ID_CODE] * 2)
self.assertEqual(ret, [ret_ir] * 2)
# ID CODE
with self.assertRaises(ValueError):
self.chip["JTAG"].scan_dr("0" * 32 * 2)
ret = self.chip["JTAG"].scan_dr(["0" * 32] * 2, readback=False)
self.assertEqual(ret, None)
id_code = BitLogic.from_value(0x149B51C3, fmt="I")
ret = self.chip["JTAG"].scan_dr(["0" * 32] * 2)
self.assertEqual(ret, [id_code] * 2)
# BYPASS + ID CODE
bypass_code = BitLogic("0")
ret = self.chip["JTAG"].scan_ir([ID_CODE, BYPASS])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip["JTAG"].scan_dr(["0" * 32, "1"])
self.assertEqual(ret, [id_code, bypass_code])
ret = self.chip["JTAG"].scan_ir([BYPASS, ID_CODE])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip["JTAG"].scan_dr(["1", "0" * 32])
self.assertEqual(ret, [bypass_code, id_code])
# DEBUG
ret = self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
self.assertEqual(ret, [ret_ir] * 2)
self.chip["JTAG"].scan_dr(["1" * 32, "0" * 1 + "1" * 30 + "0" * 1])
ret = self.chip["JTAG"].scan_dr(["0" * 32, "1" * 32])
self.assertEqual(ret, [BitLogic("1" * 32), BitLogic("0" * 1 + "1" * 30 + "0" * 1)])
ret = self.chip["JTAG"].scan_dr(["0" * 32, "0" * 32])
self.assertEqual(ret, [BitLogic("0" * 32), BitLogic("1" * 32)])
# SHIT IN DEV REG/DEBUG
self.chip["JTAG"].scan_dr([self.chip["DEV1"][:], self.chip["DEV2"][:]])
# GPIO RETURN
dev1ret.frombytes(self.chip["GPIO_DEV1"].get_data())
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
self.assertFalse(dev1ret[:] == self.chip["DEV2"][:])
dev1ret.frombytes(self.chip["GPIO_DEV2"].get_data())
self.assertEqual(dev1ret[:], self.chip["DEV2"][:])
# JTAG RETURN
ret = self.chip["JTAG"].scan_dr(["0" * 32, "0" * 32])
dev1ret.set(ret[0])
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
dev1ret.set(ret[1])
self.assertEqual(dev1ret[:], self.chip["DEV2"][:])
# REPEATING REGISTER
self.chip["JTAG"].scan_dr([self.chip["DEV"][:]], word_size=len(self.chip["DEV"][:]))
ret1 = self.chip["JTAG"].scan_dr([self.chip["DEV"][:]], word_size=len(self.chip["DEV"][:]))
self.chip["JTAG"].scan_dr([self.chip["DEV1"][:], self.chip["DEV2"][:]])
ret2 = self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
ret3 = self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
self.assertEqual(ret1[:], ret2[:])
self.assertEqual(ret2[:], ret3[:])
# REPEATING SETTING
self.chip["JTAG"].scan_dr(["1" * 32 + "0" * 32])
ret = self.chip["JTAG"].scan_dr(["0" * 32 + "0" * 32])
self.chip["DEV"].set(ret[0])
self.assertEqual(self.chip["DEV"][:], BitLogic("1" * 32 + "0" * 32))
self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
ret = self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
self.chip["DEV"].set(ret[0])
self.assertEqual(self.chip["DEV"][:], self.chip["DEV1"][:] + self.chip["DEV2"][:])
# BYPASS AND DEBUG REGISTER
self.chip["fifo1"].reset()
self.chip["fifo2"].reset()
fifo_size = self.chip["fifo1"].get_fifo_size()
self.assertEqual(fifo_size, 0)
# Generate some data
data_string = []
data = np.power(range(20), 6)
for i in range(len(data)):
s = str(bin(data[i]))[2:]
data_string.append("0" * (32 - len(s)) + s)
# Bypass first device, put data in the debug register of the second device
self.chip["JTAG"].scan_ir([DEBUG, BYPASS])
for i in range(len(data_string)):
self.chip["JTAG"].scan_dr([data_string[i], "1"])
fifo_size = self.chip["fifo1"].get_fifo_size()
self.assertEqual(fifo_size, len(data_string) * 4)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertListEqual(list(data), list(fifo_tap1_content))
self.assertNotEqual(list(data), list(fifo_tap2_content))
# empty fifos
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
# Bypass second device, put data in the debug register of the first device
self.chip["JTAG"].scan_ir([BYPASS, DEBUG])
for i in range(len(data_string)):
self.chip["JTAG"].scan_dr(["1", data_string[i]])
fifo_size = self.chip["fifo1"].get_fifo_size()
self.assertEqual(fifo_size, len(data_string) * 4)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertNotEqual(list(data), list(fifo_tap1_content))
self.assertListEqual(list(data), list(fifo_tap2_content))
# TEST OF SENDING MULTIPLE WORDS WITH SCAN_DR FUNCTION
self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
self.chip["JTAG"].set_data([0x00] * 100)
self.chip["JTAG"].set_command("DATA")
self.chip["JTAG"].SIZE = 100 * 8
self.chip["JTAG"].start()
while not self.chip["JTAG"].READY:
pass
# empty fifos
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.chip["JTAG"].scan_ir([DEBUG, BYPASS])
self.chip["JTAG"].scan_dr([BitLogic("0" * 24 + "10101101"), BitLogic("1")] * 15, word_size=33)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertListEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap1_content))
self.assertNotEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap2_content))
# change value of debug registers
self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
self.chip["JTAG"].scan_dr(["0" * 32, "0" * 32])
# empty fifos
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.chip["JTAG"].scan_ir([BYPASS, DEBUG])
self.chip["JTAG"].scan_dr([BitLogic("1"), BitLogic("0" * 24 + "10101101")] * 15, word_size=33)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertNotEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap1_content))
self.assertListEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap2_content))
# TEST OF SENDING MULTIPLE WORDS BY WRITING DIRECTLY IN JTAG MODULE MEMORY
# The ring register (DEBUG register) is 32 bits long, so the data have to be arranged like this :
# [WORD1(dev1) WORD1(dev2) WORD2(dev1) WORD2(dev2) ...]
data = np.byte(
[
0x01,
0x02,
0x03,
0x04,
0x02,
0x04,
0x06,
0x08,
0x11,
0x12,
0x13,
0x14,
0x12,
0x14,
0x16,
0x18,
0x21,
0x22,
0x23,
0x24,
0x22,
0x24,
0x26,
0x28,
0x31,
0x32,
0x33,
0x34,
0x32,
0x34,
0x36,
0x38,
0x41,
0x42,
0x43,
0x44,
0x42,
0x44,
0x46,
0x48,
]
)
device_number = 2
word_size_bit = 32
word_count = 5
self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
# empty fifo
self.chip["fifo1"].get_data()
self.chip["fifo2"].get_data()
self.chip["JTAG"].set_data(data)
self.chip["JTAG"].SIZE = word_size_bit * device_number
self.chip["JTAG"].set_command("DATA")
self.chip["JTAG"].WORD_COUNT = word_count
self.chip["JTAG"].start()
while not self.chip["JTAG"].READY:
pass
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
expected_result_tap1 = [
int("0x01020304", 16),
int("0x11121314", 16),
int("0x21222324", 16),
int("0x31323334", 16),
int("41424344", 16),
]
expected_result_tap2 = [
int("0x02040608", 16),
int("0x12141618", 16),
int("0x22242628", 16),
int("0x32343638", 16),
int("42444648", 16),
]
self.assertListEqual(expected_result_tap1, list(fifo_tap1_content))
self.assertListEqual(expected_result_tap2, list(fifo_tap2_content))
def __init__(self, driver, conf):
StdRegister.__init__(self, driver, conf)
class si570(HardwareLayer):
def __init__(self, intf, conf):
si570_reg = {
"name":
"Si570",
"type":
"StdRegister",
"driver":
"none",
"size":
48,
"fields": [
{
"name": "RFREQ",
"size": 38,
"offset": 37
},
{
"name": "N1",
"size": 7,
"offset": 44
},
{
"name": "HS_DIV",
"size": 3,
"offset": 47
},
],
}
super(si570, self).__init__(intf, conf)
self._base_addr = conf["base_addr"]
self._reg = StdRegister(driver=None, conf=si570_reg)
self._freq = conf["init"]
def init(self):
super(si570, self).init()
self.frequency_change(float(self._init["frequency"]))
def reset(self):
self._intf.write(0xBA, [135])
RECALL = self._intf.read(0xBA, 1)
self._intf.write(0xBA, [135] + [RECALL[0] | 0b1])
def frequency_change(self, freq): # freq in MHz
f0 = 156.25
self.reset()
HS_DIV, N1, RFREQ = self.read_registers()
fxtal = float(f0 * HS_DIV * N1) / (float(RFREQ) / 2**28)
new_fdco = freq * HS_DIV * N1
if 4850.0 > new_fdco or new_fdco > 5670.0:
logger.debug(
"Si570: large frequency change, recalculating HSDIV, N1")
found_new_values = False
HS_DIV_avaiable = [11, 9, 7, 6, 5, 4]
N1_avaiable = list(range(2, 129, 2))
N1_avaiable.insert(0, 1)
for hs in HS_DIV_avaiable:
for n in N1_avaiable:
fdco = freq * 1e6 * hs * n
if (fdco >= 4.85e9) & (
fdco <=
5.67e9): # fdco range defined by manufacturer
HS_DIV = hs
N1 = n
found_new_values = True
if found_new_values:
break
else: # if correct HS_DIV and N1 were not found
raise ValueError(
"The Si570 reference frequency is too low or to high")
new_fdco = freq * HS_DIV * N1
new_RFREQ_freq = new_fdco / fxtal
new_RFREQ = int(new_RFREQ_freq * 2**28)
self.modify_register(HS_DIV, N1, new_RFREQ)
logger.info("Changed Si570 reference frequency to %s MHz",
new_fdco / (HS_DIV * N1))
def modify_register(self, HS_DIV, N1, RFREQ):
# Preparation of the array that needs to be send
self._reg["HS_DIV"] = HS_DIV - 4
self._reg["N1"] = N1 - 1
self._reg["RFREQ"] = RFREQ
self._intf.write(0xBA, [137])
dco_freeze = self._intf.read(0xBA, 1)
self._intf.write(0xBA, [135])
new_freq_flag = self._intf.read(0xBA, 1)
# Freeze the DCO
self._intf.write(0xBA, [137] + [dco_freeze[0] | 0b10000])
# Write the new frequency configuration
self._intf.write(0xBA, [7] + self._reg.tobytes().tolist())
# Unfreeze the DCO
self._intf.write(0xBA, [137] + [dco_freeze[0] & 0b01111])
# Assert the NewFreq bit
self._intf.write(0xBA, [135] + [new_freq_flag[0] | 0b01000000])
def read_registers(self):
self._intf.write(0xBA, [7])
reg_val = self._intf.read(0xBA, 6)
HS_DIV = (reg_val[0] & 0xE0) >> 5
HS_DIV += 4
N1 = ((reg_val[0] & 0x1F) << 2) | ((reg_val[1] & 0xC0) >> 6)
N1 += 1
RFREQ = (((reg_val[1] & 0x3F) << 32)
| reg_val[2] << 24
| reg_val[3] << 16
| reg_val[4] << 8
| reg_val[5])
return HS_DIV, N1, RFREQ
def test_gpio(self):
ID_CODE = BitLogic('0010')
BYPASS = BitLogic('1111')
DEBUG = BitLogic('1000')
ret_ir = BitLogic('0101')
# TEST REG INIT
dev1ret = StdRegister(driver=None, conf=yaml.load(gpio_yaml))
dev1ret.init()
dev1ret['F1'] = 0x1
dev1ret['F2'] = 0x2f
dev1ret['F3'] = 0x2
dev1ret['F4'] = 0x17cf4
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.chip['DEV1']['F2'] = 0
self.assertFalse(dev1ret[:] == self.chip['DEV1'][:])
self.chip.set_configuration(init_yaml)
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.chip['jtag'].reset()
# IR CODE
ret = self.chip['jtag'].scan_ir([ID_CODE] * 2)
self.assertEqual(ret, [ret_ir] * 2)
# ID CODE
id_code = BitLogic.from_value(0x149B51C3, fmt='I')
ret = self.chip['jtag'].scan_dr(['0' * 32] * 2)
self.assertEqual(ret, [id_code] * 2)
# BYPASS + ID CODE
bypass_code = BitLogic('0')
ret = self.chip['jtag'].scan_ir([ID_CODE, BYPASS])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip['jtag'].scan_dr(['0' * 32, '1'])
self.assertEqual(ret, [id_code, bypass_code])
ret = self.chip['jtag'].scan_ir([BYPASS, ID_CODE])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip['jtag'].scan_dr(['1', '0' * 32])
self.assertEqual(ret, [bypass_code, id_code])
# DEBUG
ret = self.chip['jtag'].scan_ir([DEBUG, DEBUG])
self.assertEqual(ret, [ret_ir] * 2)
self.chip['jtag'].scan_dr(['1' * 32, '0' * 1 + '1' * 30 + '0' * 1])
ret = self.chip['jtag'].scan_dr(['0' * 32, '1' * 32])
self.assertEqual(ret, [BitLogic('1' * 32), BitLogic('0' * 1 + '1' * 30 + '0' * 1)])
ret = self.chip['jtag'].scan_dr(['0' * 32, '0' * 32])
self.assertEqual(ret, [BitLogic('0' * 32), BitLogic('1' * 32)])
# SHIT IN DEV REG/DEBUG
self.chip['jtag'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
# GPIO RETURN
dev1ret.frombytes(self.chip['gpio_dev1'].get_data())
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.assertFalse(dev1ret[:] == self.chip['DEV2'][:])
dev1ret.frombytes(self.chip['gpio_dev2'].get_data())
self.assertEqual(dev1ret[:], self.chip['DEV2'][:])
# JTAG RETURN
ret = self.chip['jtag'].scan_dr(['0' * 32, '0' * 32])
dev1ret.set(ret[0])
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
dev1ret.set(ret[1])
self.assertEqual(dev1ret[:], self.chip['DEV2'][:])
# REPEATING REGISTER
self.chip['jtag'].scan_dr([self.chip['DEV'][:]])
ret1 = self.chip['jtag'].scan_dr([self.chip['DEV'][:]])
self.chip['jtag'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
ret2 = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]])
ret3 = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]])
self.assertEqual(ret1[:], ret2[:])
self.assertEqual(ret2[:], ret3[:])
# REPEATING SETTING
self.chip['jtag'].scan_dr(['1' * 32 + '0' * 32])
ret = self.chip['jtag'].scan_dr(['0' * 32 + '0' * 32])
self.chip['DEV'].set(ret[0])
self.assertEqual(self.chip['DEV'][:], BitLogic('0' * 32 + '1' * 32))
self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]])
ret = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]])
self.chip['DEV'].set(ret[0])
self.assertEqual(self.chip['DEV'][:], self.chip['DEV1'][:] + self.chip['DEV2'][:])