def write(self, size=-1):
if size == -1:
size = self._conf["seq_size"]
bv = bitarray(self._conf["seq_width"] * size)
for i in xrange(size):
for track in self._conf['tracks']:
bit = 0
if self._conf["seq_width"] >= 8:
bit = i * self._conf["seq_width"] + self._conf["seq_width"] - 1 - track['position']
elif self._conf["seq_width"] == 4:
if i % 2 == 0:
bit = (i + 1) * self._conf["seq_width"] + self._conf["seq_width"] - 1 - track['position']
else:
bit = (i - 1) * self._conf["seq_width"] + self._conf["seq_width"] - 1 - track['position']
else:
raise NotImplementedError("To be implemented.")
bv[bit] = self._tracks[track['name']][i]
#ba = utils.bitvector_to_byte_array(bv)
ba = utils.bitarray_to_byte_array(bv)
#print 'ba1', ba
ba = ba[::-1]
#print 'ba2', ba
#print 'bv', bv[:32]
#for track in self._conf['tracks']:
# print track['name'], track['position'], self._tracks[track['name']][:32].to01(), len(self._tracks[track['name']])
self._drv.set_data(ba) # TODO: this probably has to be done different way
def write(self, size=-1):
if size == -1:
size = self._conf["seq_size"]
bv = bitarray(self._conf["seq_width"] * size)
for i in xrange(size):
for track in self._conf['tracks']:
bit = 0
if self._conf["seq_width"] >= 8:
bit = i * self._conf["seq_width"] + self._conf["seq_width"] - 1 - track['position']
elif self._conf["seq_width"] == 4:
if i % 2 == 0:
bit = (i + 1) * self._conf["seq_width"] + self._conf["seq_width"] - 1 - track['position']
else:
bit = (i - 1) * self._conf["seq_width"] + self._conf["seq_width"] - 1 - track['position']
else:
raise NotImplementedError("To be implemented.")
bv[bit] = self._tracks[track['name']][i]
# ba = utils.bitvector_to_byte_array(bv)
ba = utils.bitarray_to_byte_array(bv)
# print 'ba1', ba
ba = ba[::-1]
# print 'ba2', ba
# print 'bv', bv[:32]
# for track in self._conf['tracks']:
# print track['name'], track['position'], self._tracks[track['name']][:32].to01(), len(self._tracks[track['name']])
self._drv.set_data(ba) # TODO: this probably has to be done different way
def write(self):
"""
to call start() automatically, set yaml file as follows:
registers:
- name : CCPD_PCB
type : StdRegister
hw_driver : CCPD_PCB_SPI
size : 32
auto_start : True <------ add this
fields: ......
"""
reg = self._construct_reg()
ba = utils.bitarray_to_byte_array(reg)
self._drv.set_data(ba)
if "auto_start" in self._conf:
if self._conf["auto_start"]:
self._drv.start()
def write(self, size=-1):
if size == -1:
size = self._conf["seq_size"]
bv = bitarray(self._conf["seq_width"] * size)
for i in range(size):
for track in self._conf['tracks']:
bit = 0
if self._conf["seq_width"] >= 8:
bit = i * self._conf["seq_width"] + self._conf["seq_width"] - 1 - track['position']
elif self._conf["seq_width"] == 4:
if i % 2 == 0:
bit = (i + 1) * self._conf["seq_width"] + self._conf["seq_width"] - 1 - track['position']
else:
bit = (i - 1) * self._conf["seq_width"] + self._conf["seq_width"] - 1 - track['position']
else:
raise NotImplementedError("To be implemented.")
bv[bit] = self._tracks[track['name']][i]
ba = utils.bitarray_to_byte_array(bv)
ba = ba[::-1]
# TODO: this probably has to be done different way
self._drv.set_data(ba)
def tobytes(self):
reg = self._construct_reg()
return utils.bitarray_to_byte_array(reg)
def tobytes(self):
reg = self._construct_reg()
return utils.bitarray_to_byte_array(reg)