def step(self): opcode = self.fetch() instruction = self.__instructions[opcode] decinc = SPC700Instruction( self.PC - 1, instruction, self.io.RAM[self.PC - 1:self.PC - 1 + instruction["bytes"]]) instruction["fp"]() print("{:04X}: {:10} {:20} {}".format( decinc.offset, "{:10}".format(" ".join(["{:02x}".format(b) for b in decinc.bytes])), decinc.tostring(True), "A: {:02X} X: {:02X} Y: {:02X} SP: {:04X} {}".format( self.A, self.X, self.Y, (1 << 8) | self.S, " ".join([ "{}: {}".format("CZIHBPVN"[i], bitget(self.P.value, i)) for i in range(8) ]))))
def write(self, address, data): self.step() if address in self.ports: port = self.ports[address] if port.writable: if port.target == "TEST": pass ## TODO : to be implemented eventually but nice to have elif port.target == "CONTROL": if bitget(data, 0) == 0: self.timer0.enable = False else: self.timer0.enable = True self.timer0.stage1 = 0 self.timer0.stage2 = 0 if bitget(data, 1) == 0: self.timer1.enable = False else: self.timer1.enable = True self.timer1.stage1 = 0 self.timer1.stage2 = 0 if bitget(data, 2) == 0: self.timer2.enable = False else: self.timer2.enable = True self.timer2.stage1 = 0 self.timer2.stage2 = 0 if bitget(data, 4) == 1: self.apu0 = 0 self.apu1 = 0 if bitget(data, 5) == 1: self.apu2 = 0 self.apu3 = 0 self.iplROMEnable = bitget(data, 7) == 1 elif port.target == "AUXIO4": self.aux4 = data elif port.target == "AUXIO5": self.aux5 = data elif port.target == "T0TARGET": self.timer0.target = data elif port.target == "T1TARGET": self.timer1.target = data elif port.target == "T2TARGET": self.timer2.target = data else: pass else: self.RAM[address] = data
def N(self): return bitget(self.value, 7)
def V(self): return bitget(self.value, 6)
def P(self): return bitget(self.value, 5)
def B(self): return bitget(self.value, 4)
def H(self): return bitget(self.value, 3)
def I(self): return bitget(self.value, 2)
def Z(self): return bitget(self.value, 1)
def C(self): return bitget(self.value, 0)