def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
srcop = self.src_operand
srcval = simstate.rhs(iaddr, srcop)
tgt = self.target.absolute_address_value
truetgt = simstate.resolve_literal_address(iaddr, tgt)
falsetgt = simstate.programcounter.add_offset(8)
simstate.increment_programcounter()
expr = str(srcval) + "< 0"
if truetgt.is_undefined:
raise SU.CHBSimError(
simstate, iaddr,
"bltz: target address cannot be resolved: " + str(tgt))
if srcval.is_undefined:
result = SV.simUndefinedBool
elif srcval.is_literal:
v = SV.mk_simvalue(srcval.literal_value)
if v.to_signed_int() < 0:
result = SV.simtrue
else:
result = SV.simfalse
elif srcval.is_symbol:
srcval = cast(SSV.SimSymbol, srcval)
result = srcval.is_negative
else:
result = SV.simUndefinedBool
if result.is_defined:
if result.is_true:
simstate.simprogramcounter.set_delayed_programcounter(truetgt)
else:
simstate.simprogramcounter.set_delayed_programcounter(falsetgt)
return SU.simbranch(iaddr, simstate, truetgt, falsetgt, expr,
result)
else:
raise SU.CHBSimBranchUnknownError(simstate, iaddr, truetgt,
falsetgt, "bltz: " + expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
srcop = self.src_operand
tgtop = self.target
srcval = simstate.rhs(iaddr, srcop)
truetgt = simstate.resolve_literal_address(
iaddr, tgtop.absolute_address_value)
falsetgt = simstate.programcounter.add_offset(8)
simstate.increment_programcounter()
expr = str(srcval) + " < 0"
simstate.registers["ra"] = falsetgt
if truetgt.is_undefined:
raise SU.CHBSimError(
simstate, iaddr,
"bltzal: target address for function call cannot be resolved: "
+ str(self.target))
if srcval.is_undefined:
result = SV.simUndefinedBool
elif srcval.is_literal:
v = SV.mk_simvalue(srcval.literal_value)
if v.to_signed_int() < 0:
result = SV.simtrue
else:
result = SV.simfalse
else:
result = SV.simUndefinedBool
if result.is_defined:
if result.is_true:
simstate.simprogramcounter.set_delayed_programcounter(truetgt)
else:
simstate.simprogramcounter.set_delayed_programcounter(falsetgt)
return SU.simbranchcall(iaddr, simstate, truetgt, falsetgt, expr,
result)
else:
raise SU.CHBSimBranchUnknownError(simstate, iaddr, truetgt,
falsetgt, "bltzal: " + expr)
def simulate(self, iaddr: str, simstate: "SimulationState") -> str:
src1op = self.src1_operand
src2op = self.src2_operand
src1val = simstate.rhs(iaddr, src1op)
src2val = simstate.rhs(iaddr, src2op)
tgt = self.target
truetgt = simstate.resolve_literal_address(iaddr, tgt.absolute_address_value)
falsetgt = simstate.programcounter.add_offset(8)
simstate.increment_programcounter()
if truetgt.is_undefined:
raise SU.CHBSimError(
simstate,
iaddr,
"bne: branch target address cannot be resolved: " + str(tgt))
if src1val.is_undefined or src2val.is_undefined:
result = SV.simUndefinedBool
elif src1val.is_literal and src2val.is_literal:
if src1val.literal_value == src2val.literal_value:
result = SV.simfalse
else:
result = SV.simtrue
elif src1val.is_address and src2val.is_address:
src1val = cast(SSV.SimAddress, src1val)
src2val = cast(SSV.SimAddress, src2val)
if src1val.base == src2val.base:
if src1val.offsetvalue == src2val.offsetvalue:
result = SV.simfalse
else:
result = SV.simtrue
else:
result = SV.simtrue
elif src1val.is_address and src2val.is_literal:
if src2val.literal_value == 0:
result = SV.simtrue
else:
result = SV.simUndefinedBool
elif src1val.is_file_pointer and src2val.is_literal:
if src2val.literal_value == 0:
result = SV.simtrue
else:
result = SV.simUndefinedBool
elif src1val.is_string_address and src2val.is_literal:
if src2val.literal_value == 0:
result = SV.simtrue
else:
result = SV.simUndefinedBool
elif src1val.is_symbol_table_handle and src2val.is_literal:
if src2val.literal_value == 0:
result = SV.simtrue
else:
result = SV.simUndefinedBool
elif src1val.is_dynamic_link_symbol and src2val.is_literal:
if src2val.literal_value == 0:
result = SV.simtrue
else:
result = SV.simUndefinedBool
elif src1val.is_string_address and src2val.is_string_address:
v1 = cast(SSV.SimStringAddress, src1val)
v2 = cast(SSV.SimStringAddress, src2val)
if v1.stringval == v2.stringval:
result = SV.simfalse
else:
result = SV.simtrue
else:
result = SV.simUndefinedBool
if result.is_defined:
if result.is_true:
simstate.simprogramcounter.set_delayed_programcounter(truetgt)
else:
simstate.simprogramcounter.set_delayed_programcounter(falsetgt)
expr = str(src1val) + ' != ' + str(src2val)
return SU.simbranch(iaddr, simstate, truetgt, falsetgt, expr, result)
else:
raise SU.CHBSimBranchUnknownError(
simstate,
iaddr,
truetgt,
falsetgt,
'bne: ' + str(src1val) + ' != ' + str(src2val))
def unknowntgt() -> NoReturn:
simstate.add_logmsg("warning",
iaddr + ": bgez branch unknown: " + expr)
raise SU.CHBSimBranchUnknownError(simstate, iaddr, truetgt,
falsetgt, ("bgez: " + expr))
