def gen_hdl_regrdmux_dff(root, module, pfx, isigs):
proc = HDLSync(root.h_bus['clk'], None)
proc.name = '{}RegRdMux_DFF'.format(pfx)
gen_hdl_locregrd2regrd(proc.sync_stmts, isigs)
# proc.sync_stmts.append(HDLAssign(isigs.RegWrOK, isigs.Loc_RegWrOK))
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_strobeseq(root, module, isigs):
proc = HDLSync(root.h_bus['clk'], None)
proc.name = 'StrobeSeq'
proc.sync_stmts.append(
HDLAssign(
isigs.Loc_VMERdMem,
HDLConcat(HDLSlice(isigs.Loc_VMERdMem, 0, 2), root.h_bus['rd'])))
proc.sync_stmts.append(
HDLAssign(
isigs.Loc_VMEWrMem,
HDLConcat(HDLSlice(isigs.Loc_VMEWrMem, 0, None),
root.h_bus['wr'])))
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def add_read_reg_process(root, module, isigs):
# Register read
rd_data = root.h_reg_rdat_int
rd_ack = root.h_rd_ack1_int
rdproc = HDLSync(root.h_bus['clk'], root.h_bus['rst'])
module.stmts.append(rdproc)
rdproc.rst_stmts.append(HDLAssign(rd_ack, bit_0))
rdproc.rst_stmts.append(
HDLAssign(rd_data, HDLReplicate(bit_x, root.c_word_bits)))
rdproc.sync_stmts.append(
HDLAssign(rd_data, HDLReplicate(bit_x, root.c_word_bits)))
rd_if = HDLIfElse(HDLAnd(HDLEq(isigs.rd_int, bit_1), HDLEq(rd_ack, bit_0)))
rdproc.sync_stmts.append(rd_if)
rd_if.then_stmts.append(HDLAssign(rd_ack, bit_1))
rd_if.else_stmts.append(HDLAssign(rd_ack, bit_0))
def add_read_reg(s, n, off):
for f in n.children:
if n.access in ['wo', 'rw']:
src = f.h_reg
elif n.access == 'ro':
src = f.h_iport
elif n.access == 'cst':
src = HDLConst(f.preset, f.c_rwidth)
else:
raise AssertionError
reg, dat = field_decode(root, n, f, off, src, rd_data)
if reg is None:
continue
s.append(HDLAssign(dat, reg))
def add_read(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
if n.access != 'wo':
add_read_reg(s, n, off)
elif isinstance(n, tree.Submap):
pass
elif isinstance(n, tree.Array):
s.append(HDLComment("RAM {}".format(n.name)))
else:
# Blocks have been handled.
raise AssertionError
then_stmts = []
add_decoder(root, then_stmts, root.h_bus.get('adr', None), root, add_read)
rd_if.then_stmts.extend(then_stmts)
def add_write_process(root, module, isigs):
# Register write
wrproc = HDLSync(root.h_bus['clk'], root.h_bus['rst'])
module.stmts.append(wrproc)
if root.h_ram_wr_dly is not None:
wrproc.rst_stmts.append(HDLAssign(root.h_ram_wr_dly, bit_0))
wr_if = HDLIfElse(
HDLAnd(HDLEq(isigs.wr_int, bit_1), HDLEq(isigs.wr_ack, bit_0)))
wr_if.else_stmts.append(HDLAssign(isigs.wr_ack, bit_0))
wr_data = root.h_bus['dati']
def add_write_reg(s, n, off):
for f in n.children:
# Reset code
if f.h_reg is not None:
v = 0 if f.preset is None else f.preset
cst = HDLConst(v, f.c_iowidth if f.c_iowidth != 1 else None)
wrproc.rst_stmts.append(HDLAssign(f.h_reg, cst))
# Assign code
if f.hdl_type == 'reg':
r = f.h_reg
elif f.hdl_type == 'wire':
r = f.h_oport
else:
raise AssertionError
reg, dat = field_decode(root, n, f, off, r, wr_data)
if reg is None:
continue
s.append(HDLAssign(reg, dat))
if f.h_wport is not None:
s.append(HDLAssign(f.h_wport, bit_1))
wrproc.rst_stmts.append(HDLAssign(f.h_wport, bit_0))
wrproc.sync_stmts.append(HDLAssign(f.h_wport, bit_0))
def add_write(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
if n.access in ['wo', 'rw']:
add_write_reg(s, n, off)
elif isinstance(n, tree.Submap):
s.append(HDLComment("Submap {}".format(n.name)))
if n.c_interface == 'wb-32-be':
wrproc.rst_stmts.append(HDLAssign(n.h_wr, bit_0))
wr_if.then_stmts.append(HDLAssign(n.h_wr, bit_0))
s.append(HDLAssign(n.h_wr, bit_1))
s.append(HDLAssign(isigs.wr_ack, n.h_bus['ack']))
return
elif n.c_interface == 'sram':
s.append(HDLAssign(n.h_wr_o, bit_1))
return
else:
raise AssertionError
elif isinstance(n, tree.Array):
# TODO: handle list of registers!
r = n.children[0]
wrproc.rst_stmts.append(HDLAssign(r.h_sig_wr, bit_0))
wr_if.else_stmts.append(HDLAssign(r.h_sig_wr, bit_0))
s2 = HDLIfElse(HDLEq(root.h_ram_wr_dly, bit_0))
s.append(s2)
s2.then_stmts.append(HDLAssign(r.h_sig_wr, bit_1))
s2.then_stmts.append(HDLAssign(root.h_ram_wr_dly, bit_1))
s2.else_stmts.append(HDLAssign(root.h_ram_wr_dly, bit_0))
s2.else_stmts.append(HDLAssign(isigs.wr_ack, bit_1))
return
else:
# Including blocks.
raise AssertionError
# All the write are ack'ed (including the write to unassigned
# addresses)
s.append(HDLAssign(isigs.wr_ack, bit_1))
then_stmts = []
add_decoder(root, then_stmts, root.h_bus.get('adr', None), root, add_write)
wr_if.then_stmts.extend(then_stmts)
wrproc.sync_stmts.append(wr_if)
def gen_hdl_memwrmux_dff(root, module, isigs, pfx):
proc = HDLSync(root.h_bus['clk'], None)
proc.name = pfx + 'MemWrMux_DFF'
gen_hdl_locmem2mem_wr(root, module, isigs, proc.sync_stmts)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_cregrdmux_dff(root, module, isigs, pfx):
proc = HDLSync(root.h_bus['clk'], None)
proc.name = '{}CRegRdMux_DFF'.format(pfx)
gen_hdl_cregrdmux_asgn(proc.sync_stmts, isigs)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))