def testFileSet(self): project = Project() expected_files = [] for libname in self.project_structure.keys(): files = self.project_structure[libname] for path in files: expected_files.append(os.path.basename(path)) project.add_file(path, libname) self.assertEqual( sorted(expected_files), sorted([os.path.basename(f.path) for f in project.get_files()]), )
# The constraints are added to the project using the add_constraints method. # The optional 'flow' argument is used to explicitly identify which synthesis # flow the constraints are intended for (the default is to infer supported # flows from the file extension). # project.add_constraints('axi_lite_slave_example.xdc', flow='vivado') # Synthesis generics can be assigned via the add_generic command, in this # example we set the data_Width generic to 32: project.add_generic('data_width', 32) # Source files for the component are added to the project. The Project # 'add_file' method accepts a file path and library name, if no library is # specified it will default to 'work'. Other file attributes are available but # not covered in this example. project.add_file('axi_lite_slave_example.v', library='lib_example') # When adding the testbench file we supply a 'synthesise' attribute and set it # to 'False', this tells the synthesis tool not to try to synthesise this file. # If not specified, 'synthesise' will default to 'True' project.add_file( 'tb_axi_lite_slave_example.v', library='lib_tb_example', synthesise=False ) if __name__ == '__main__': interactive = True # Set True to load the ChipTools CLI if interactive:
# The constraints are added to the project using the add_constraints method. # The optional 'flow' argument is used to explicitly identify which synthesis # flow the constraints are intended for (the default is to infer supported # flows from the file extension). project.add_constraints('max_hold.xdc', flow='vivado') project.add_constraints('max_hold.ucf', flow='ise') # Synthesis generics can be assigned via the add_generic command, in this # example we set the data_Width generic to 3: project.add_generic('data_width', 3) # Source files for the max_hold component are added to the project. The Project # 'add_file' method accepts a file path and library name, if no library is # specified it will default to 'work'. Other file attributes are available but # not covered in this example. project.add_file('max_hold.vhd', library='lib_max_hold') project.add_file('pkg_max_hold.vhd', library='lib_max_hold') # When adding the testbench file we supply a 'synthesise' attribute and set it # to 'False', this tells the synthesis tool not to try to synthesise this file. # If not specified, 'synthesise' will default to 'True' project.add_file( 'tb_max_hold.vhd', library='lib_tb_max_hold', synthesise=False ) interactive = False if interactive: # ChipTools provides a command line interface to allow you to perform