def __init__(self, cwtype, scope, oa):
# Setup FPGA partial configuration dataZ
self.prCon = pr.PartialReconfigConnection()
self.prEnabled = False
self.oa = oa
# Glitch width/offset
# Note that these are ints scaled by 256/100
self._width = 26
self._offset = 26
# These ranges are updated during __init__: see below
self._min_width = 0
self._max_width = 100
self._min_offset = 0
self._max_offset = 100
# Single-shot arm timing
self._ssarm = 2
# Check if we've got partial reconfiguration stuff for this scope
try:
if cwtype == "cwrev2" or cwtype == "cwcrev2":
settingprefix = "cwcrev2"
partialbasename = "s6lx25"
self.glitchPR = pr.PartialReconfigDataMulti()
elif cwtype == "cwlite":
settingprefix = "cwlite"
partialbasename = "cwlite"
self.glitchPR = pr.PartialReconfigDataMulti()
elif cwtype == "cw1200":
settingprefix = "cw1200"
partialbasename = "cw1200"
self.glitchPR = pr.PartialReconfigDataMulti()
else:
raise ValueError("Invalid ChipWhisperer Mode: %s" % cwtype)
if scope.getFWConfig().loader._release_mode != "debug":
if scope.getFWConfig().loader._release_mode == "builtin":
filelike = scope.getFWConfig().loader._bsBuiltinData
zfile = zipfile.ZipFile(filelike)
elif scope.getFWConfig().loader._release_mode == "zipfile":
fileloc = scope.getFWConfig().loader._bsZipLoc
if zipfile.is_zipfile(fileloc):
zfile = zipfile.ZipFile(fileloc, "r")
else:
logging.warning('Partial Reconfiguration DISABLED: no zip-file for FPGA')
zfile = None
else:
logging.warning('Partial Reconfiguration DISABLED: no PR data for FPGA')
zfile = None
raise ValueError("Unknown FPGA mode: %s"%scope.getFWConfig().loader._release_mode)
if zfile:
self.glitchPR.load(zfile.open("%s-glitchwidth.p" % partialbasename))
self.glitchPR.load(zfile.open("%s-glitchoffset.p" % partialbasename))
self.prEnabled = True
else:
self.prEnabled = False
else:
logging.warning('Partial Reconfiguration DISABLED: Debug bitstream mode')
self.prEnabled = False
except IOError as e:
logging.error(str(e))
self.prEnabled = False
except ValueError as e:
logging.error(str(e))
self.prEnabled = False
except OSError as e: # Also catches WindowsError
logging.error(str(e))
self.prEnabled = False
if self.prEnabled:
# Enable glitch width, check what we've got access to
self._min_width = self.glitchPR.limitList[0][0] / 2.55
self._max_width = self.glitchPR.limitList[0][1] / 2.55
self._min_offset = self.glitchPR.limitList[1][0] / 2.55
self._max_offset = self.glitchPR.limitList[1][1] / 2.55
self.setOpenADC(oa)
self.glitchSettings = GlitchSettings(self)
def __init__(self, cwtype, scope, oa):
# Setup FPGA partial configuration dataZ
self.prCon = pr.PartialReconfigConnection()
self.prEnabled = False
self.oa = oa
# Glitch width/offset
# Note that these are ints scaled by 256/100
self._width = 26
self._offset = 26
# These ranges are updated during __init__: see below
self._min_width = 0
self._max_width = 100
self._min_offset = 0
self._max_offset = 100
# Single-shot arm timing
self._ssarm = 2
self.params = Parameter(name=self.getName(), type='group').register()
self.params.addChildren([
{
'name': 'Clock Source',
'type': 'list',
'values': {
'Target IO-IN': self.CLKSOURCE0_BIT,
'CLKGEN': self.CLKSOURCE1_BIT
},
'set': self.setGlitchClkSource,
'get': self.glitchClkSource
},
{
'name': 'Glitch Width (as % of period)',
'key': 'width',
'type': 'float',
'limits': (self._min_width, self._max_width),
'step': 0.39062,
'readonly': True,
'set': self.setGlitchWidth,
'get': self.getGlitchWidth
},
{
'name': 'Glitch Width (fine adjust)',
'key': 'widthfine',
'type': 'int',
'limits': (-255, 255),
'set': self.setGlitchWidthFine,
'get': self.getGlitchWidthFine
},
{
'name': 'Glitch Offset (as % of period)',
'key': 'offset',
'type': 'float',
'limits': (self._min_offset, self._max_offset),
'step': 0.39062,
'readonly': True,
'set': self.setGlitchOffset,
'get': self.getGlitchOffset
},
{
'name': 'Glitch Offset (fine adjust)',
'key': 'offsetfine',
'type': 'int',
'limits': (-255, 255),
'set': self.setGlitchOffsetFine,
'get': self.getGlitchOffsetFine
},
{
'name': 'Glitch Trigger',
'type': 'list',
'values': {
'Ext Trigger:Continous': 1,
'Manual': 0,
'Continuous': 2,
'Ext Trigger:Single-Shot': 3
},
'set': self.setGlitchTrigger,
'get': self.glitchTrigger
},
{
'name': 'Single-Shot Arm',
'type': 'list',
'key': 'ssarm',
'values': {
'Before Scope Arm': 1,
'After Scope Arm': 2
},
'set': self.setArmTiming,
'get': self.getArmTiming
},
{
'name': 'Ext Trigger Offset',
'type': 'int',
'range': (0, 50000000),
'set': self.setTriggerOffset,
'get': self.triggerOffset
},
{
'name': 'Repeat',
'type': 'int',
'limits': (1, 255),
'set': self.setNumGlitches,
'get': self.numGlitches
},
{
'name': 'Manual Trigger / Single-Shot Arm',
'type': 'action',
'action': self.glitchManual
},
{
'name': 'Output Mode',
'type': 'list',
'values': {
'Clock XORd': 0,
'Clock ORd': 1,
'Glitch Only': 2,
'Clock Only': 3,
'Enable Only': 4
},
'set': self.setGlitchType,
'get': self.glitchType
},
{
'name': 'Read Status',
'type': 'action',
'action': self.checkLocked
},
{
'name': 'Reset DCM',
'type': 'action',
'action': self.actionResetDCMs
},
])
# Check if we've got partial reconfiguration stuff for this scope
try:
if cwtype == "cwrev2" or cwtype == "cwcrev2":
settingprefix = "cwcrev2"
partialbasename = "s6lx25"
self.glitchPR = pr.PartialReconfigDataMulti()
elif cwtype == "cwlite":
settingprefix = "cwlite"
partialbasename = "cwlite"
self.glitchPR = pr.PartialReconfigDataMulti()
elif cwtype == "cw1200":
settingprefix = "cw1200"
partialbasename = "cw1200"
self.glitchPR = pr.PartialReconfigDataMulti()
else:
raise ValueError("Invalid ChipWhisperer Mode: %s" % cwtype)
if scope.getFWConfig().loader._release_mode != "debug":
if scope.getFWConfig().loader._release_mode == "builtin":
filelike = scope.getFWConfig().loader._bsBuiltinData
zfile = zipfile.ZipFile(filelike)
elif scope.getFWConfig().loader._release_mode == "zipfile":
fileloc = scope.getFWConfig().loader._bsZipLoc
if zipfile.is_zipfile(fileloc):
zfile = zipfile.ZipFile(fileloc, "r")
else:
logging.warning(
'Partial Reconfiguration DISABLED: no zip-file for FPGA'
)
zfile = None
else:
logging.warning(
'Partial Reconfiguration DISABLED: no PR data for FPGA'
)
zfile = None
raise ValueError("Unknown FPGA mode: %s" %
scope.getFWConfig().loader._release_mode)
if zfile:
self.glitchPR.load(
zfile.open("%s-glitchwidth.p" % partialbasename))
self.glitchPR.load(
zfile.open("%s-glitchoffset.p" % partialbasename))
self.prEnabled = True
else:
self.prEnabled = False
else:
logging.warning(
'Partial Reconfiguration DISABLED: Debug bitstream mode')
self.prEnabled = False
except IOError as e:
logging.error(str(e))
self.prEnabled = False
except ValueError as e:
logging.error(str(e))
self.prEnabled = False
except OSError as e: # Also catches WindowsError
logging.error(str(e))
self.prEnabled = False
if self.prEnabled:
# Enable glitch width, check what we've got access to
self.findParam('width').setReadonly(False)
self._min_width = self.glitchPR.limitList[0][0] / 2.55
self._max_width = self.glitchPR.limitList[0][1] / 2.55
self.findParam('width').setLimits(
(self._min_width, self._max_width))
self.findParam('offset').setReadonly(False)
self._min_offset = self.glitchPR.limitList[1][0] / 2.55
self._max_offset = self.glitchPR.limitList[1][1] / 2.55
self.findParam('offset').setLimits(
(self._min_offset, self._max_offset))
self.setOpenADC(oa)
self.glitchSettings = GlitchSettings(self)