def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 10, units="ns").start()) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst) self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.clk, dut.rst, size=2**16)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.a_clk, 8, units="ns").start()) cocotb.fork(Clock(dut.b_clk, 10, units="ns").start()) self.axil_master = [] self.axil_master.append(AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_a"), dut.a_clk, dut.a_rst)) self.axil_master.append(AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_b"), dut.b_clk, dut.b_rst))
def __init__(self, dut): self.dut = dut s_count = int(os.getenv("PARAM_S_COUNT")) m_count = int(os.getenv("PARAM_M_COUNT")) self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 10, units="ns").start()) self.axil_master = [AxiLiteMaster(AxiLiteBus.from_prefix(dut, f"s{k:02d}_axil"), dut.clk, dut.rst) for k in range(s_count)] self.axil_ram = [AxiLiteRam(AxiLiteBus.from_prefix(dut, f"m{k:02d}_axil"), dut.clk, dut.rst, size=2**16) for k in range(m_count)]
def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk_250mhz, 4, units="ns").start()) # AXI self.address_space = AddressSpace() self.pool = self.address_space.create_pool(0, 0x8000_0000) self.axil_master = AxiLiteMaster( AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk_250mhz, dut.rst_250mhz) self.address_space.register_region(self.axil_master, 0x10_0000_0000) self.hw_regs = self.address_space.create_window( 0x10_0000_0000, self.axil_master.size) self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk_250mhz, dut.rst_250mhz, self.address_space) self.driver = mqnic.Driver() # Ethernet cocotb.start_soon(Clock(dut.sfp0_rx_clk, 6.4, units="ns").start()) self.sfp0_source = XgmiiSource(dut.sfp0_rxd, dut.sfp0_rxc, dut.sfp0_rx_clk, dut.sfp0_rx_rst) cocotb.start_soon(Clock(dut.sfp0_tx_clk, 6.4, units="ns").start()) self.sfp0_sink = XgmiiSink(dut.sfp0_txd, dut.sfp0_txc, dut.sfp0_tx_clk, dut.sfp0_tx_rst) cocotb.start_soon(Clock(dut.sfp1_rx_clk, 6.4, units="ns").start()) self.sfp1_source = XgmiiSource(dut.sfp1_rxd, dut.sfp1_rxc, dut.sfp1_rx_clk, dut.sfp1_rx_rst) cocotb.start_soon(Clock(dut.sfp1_tx_clk, 6.4, units="ns").start()) self.sfp1_sink = XgmiiSink(dut.sfp1_txd, dut.sfp1_txc, dut.sfp1_tx_clk, dut.sfp1_tx_rst) cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start()) dut.sfp_drp_rst.setimmediatevalue(0) dut.sfp_drp_do.setimmediatevalue(0) dut.sfp_drp_rdy.setimmediatevalue(0) dut.sfp0_rx_error_count.setimmediatevalue(0) dut.sfp1_rx_error_count.setimmediatevalue(0) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) dut.btnd.setimmediatevalue(0) dut.btnr.setimmediatevalue(0) dut.btnc.setimmediatevalue(0) dut.sw.setimmediatevalue(0) dut.i2c_scl_i.setimmediatevalue(1) dut.i2c_sda_i.setimmediatevalue(1) self.loopback_enable = False cocotb.start_soon(self._run_loopback())
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) # PCIe self.rc = RootComplex() self.dev = UltraScalePlusPcieDevice( # configuration options pcie_generation=3, # pcie_link_width=2, # user_clk_frequency=250e6, alignment="dword", cq_cc_straddle=False, rq_rc_straddle=False, rc_4tlp_straddle=False, enable_pf1=False, enable_client_tag=True, enable_extended_tag=False, enable_parity=False, enable_rx_msg_interface=False, enable_sriov=False, enable_extended_configuration=False, enable_pf0_msi=True, enable_pf1_msi=False, # signals user_clk=dut.clk, user_reset=dut.rst, cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc") ) self.dev.log.setLevel(logging.DEBUG) self.dev.functions[0].configure_bar(0, 16*1024*1024) self.dev.functions[0].configure_bar(1, 16*1024, io=True) self.rc.make_port().connect(self.dev) # AXI self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.clk, dut.rst, size=2**16) dut.completer_id.setimmediatevalue(0) dut.completer_id_enable.setimmediatevalue(0) # monitor error outputs self.status_error_cor_asserted = False self.status_error_uncor_asserted = False cocotb.fork(self._run_monitor_status_error_cor()) cocotb.fork(self._run_monitor_status_error_uncor())
def __init__(self, dut): self.dut = dut s_count = len(dut.axil_crossbar_inst.s_axil_awvalid) m_count = len(dut.axil_crossbar_inst.m_axil_awvalid) self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 10, units="ns").start()) self.axil_master = [ AxiLiteMaster(AxiLiteBus.from_prefix(dut, f"s{k:02d}_axil"), dut.clk, dut.rst) for k in range(s_count) ] self.axil_ram = [ AxiLiteRam(AxiLiteBus.from_prefix(dut, f"m{k:02d}_axil"), dut.clk, dut.rst, size=2**16) for k in range(m_count) ]
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) self.stat_source = AxiStreamSource( AxiStreamBus.from_prefix(dut, "s_axis_stat"), dut.clk, dut.rst) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start()) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst) self.dequeue_req_source = DequeueReqSource(DequeueReqBus.from_prefix(dut, "s_axis_dequeue_req"), dut.clk, dut.rst) self.dequeue_resp_sink = DequeueRespSink(DequeueRespBus.from_prefix(dut, "m_axis_dequeue_resp"), dut.clk, dut.rst) self.dequeue_commit_source = DequeueCommitSource(DequeueCommitBus.from_prefix(dut, "s_axis_dequeue_commit"), dut.clk, dut.rst) self.doorbell_sink = DoorbellSink(DoorbellBus.from_prefix(dut, "m_axis_doorbell"), dut.clk, dut.rst) dut.enable.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.phy_tx_clk, 6.4, units="ns").start()) cocotb.start_soon(Clock(dut.phy_rx_clk, 6.4, units="ns").start()) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst) dut.phy_rx_error_count.setimmediatevalue(0) dut.tdma_timeslot_index.setimmediatevalue(0) dut.tdma_timeslot_start.setimmediatevalue(0) dut.tdma_timeslot_active.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 10, units="ns").start()) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst) dut.reg_wr_wait.setimmediatevalue(0) dut.reg_wr_ack.setimmediatevalue(0) dut.reg_rd_data.setimmediatevalue(0) dut.reg_rd_wait.setimmediatevalue(0) dut.reg_rd_ack.setimmediatevalue(0) self.mem = mmap.mmap(-1, 16384) cocotb.fork(self.run_reg_read()) cocotb.fork(self.run_reg_write())
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start()) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst) self.irq_source = IrqSource(IrqBus.from_prefix(dut, "irq"), dut.clk, dut.rst) self.tlp_sink = PcieIfSink( PcieIfTxBus.from_prefix(dut, "tx_wr_req_tlp"), dut.clk, dut.rst) dut.requester_id.setimmediatevalue(0) dut.msix_enable.setimmediatevalue(0) dut.msix_mask.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.fork(Clock(dut.phy_tx_clk, 6.4, units="ns").start()) cocotb.fork(Clock(dut.phy_rx_clk, 6.4, units="ns").start()) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst) self.ptp_clock = PtpClock(ts_96=dut.ptp_ts_96, ts_step=dut.ptp_ts_step, clock=dut.clk, reset=dut.rst, period_ns=6.4) dut.phy_rx_error_count.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start()) # PCIe self.rc = RootComplex() self.dev = PcieIfDevice( clk=dut.clk, rst=dut.rst, rx_req_tlp_bus=PcieIfRxBus.from_prefix(dut, "rx_req_tlp"), tx_cpl_tlp_bus=PcieIfTxBus.from_prefix(dut, "tx_cpl_tlp")) self.dev.log.setLevel(logging.DEBUG) self.dev.functions[0].configure_bar(0, 16 * 1024 * 1024) self.dev.functions[0].configure_bar(1, 16 * 1024, io=True) self.rc.make_port().connect(self.dev) # AXI self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.clk, dut.rst, size=2**16) dut.completer_id.setimmediatevalue(0) # monitor error outputs self.status_error_cor_asserted = False self.status_error_uncor_asserted = False cocotb.start_soon(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def __init__(self, dut: cocotb.handle.HierarchyObject, n_sec): self.dut = dut # Sanity checks assert (self.CLOCK_FREQ_MHZ * 1e9 / fm_global.fs_rx_c).is_integer(), \ "Clock rate and fs_rx_c must have an integer relation!" # Instantiate model golden_data_directory = "../../../../../sim/matlab/verification_data/" self.model = FM_RECEIVER_MODEL(n_sec, golden_data_directory) # Connect AXI interface (IP input) self.axis_m = Axi4StreamMaster(dut, "s0_axis", dut.clk_i) # Backpressure from I2S output self.backpressure_i2s = BitDriver(dut.m0_axis_tready, dut.clk_i) # AXILite register interface self.axil_mm_m = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axi"), dut.clk_i, dut.rst_n_i, reset_active_level=False) # Variables self.tb_data_handler = TB_DATA_HANDLER() self.tb_analyzer_helper = TB_ANALYZER_HELPER(self.model, self.tb_data_handler, is_cocotb=True)
def __init__(self, dut): self.dut = dut self.BAR0_APERTURE = int(os.getenv("PARAM_BAR0_APERTURE")) self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) # PCIe self.rc = RootComplex() self.rc.max_payload_size = 0x1 # 256 bytes self.rc.max_read_request_size = 0x2 # 512 bytes self.dev = UltraScalePlusPcieDevice( # configuration options pcie_generation=3, pcie_link_width=16, user_clk_frequency=250e6, alignment="dword", cq_cc_straddle=False, rq_rc_straddle=False, rc_4tlp_straddle=False, enable_pf1=False, enable_client_tag=True, enable_extended_tag=True, enable_parity=False, enable_rx_msg_interface=False, enable_sriov=False, enable_extended_configuration=False, enable_pf0_msi=True, enable_pf1_msi=False, # signals # Clock and Reset Interface user_clk=dut.clk_250mhz, user_reset=dut.rst_250mhz, # user_lnk_up # sys_clk # sys_clk_gt # sys_reset # phy_rdy_out # Requester reQuest Interface rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, # pcie_rq_tag0 # pcie_rq_tag1 # pcie_rq_tag_av # pcie_rq_tag_vld0 # pcie_rq_tag_vld1 # Requester Completion Interface rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, # Configuration Management Interface cfg_mgmt_addr=dut.cfg_mgmt_addr, cfg_mgmt_function_number=dut.cfg_mgmt_function_number, cfg_mgmt_write=dut.cfg_mgmt_write, cfg_mgmt_write_data=dut.cfg_mgmt_write_data, cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, cfg_mgmt_read=dut.cfg_mgmt_read, cfg_mgmt_read_data=dut.cfg_mgmt_read_data, cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, # cfg_mgmt_debug_access # Configuration Status Interface # cfg_phy_link_down # cfg_phy_link_status # cfg_negotiated_width # cfg_current_speed cfg_max_payload=dut.cfg_max_payload, cfg_max_read_req=dut.cfg_max_read_req, # cfg_function_status # cfg_vf_status # cfg_function_power_state # cfg_vf_power_state # cfg_link_power_state # cfg_err_cor_out # cfg_err_nonfatal_out # cfg_err_fatal_out # cfg_local_error_out # cfg_local_error_valid # cfg_rx_pm_state # cfg_tx_pm_state # cfg_ltssm_state # cfg_rcb_status # cfg_obff_enable # cfg_pl_status_change # cfg_tph_requester_enable # cfg_tph_st_mode # cfg_vf_tph_requester_enable # cfg_vf_tph_st_mode # Configuration Received Message Interface # cfg_msg_received # cfg_msg_received_data # cfg_msg_received_type # Configuration Transmit Message Interface # cfg_msg_transmit # cfg_msg_transmit_type # cfg_msg_transmit_data # cfg_msg_transmit_done # Configuration Flow Control Interface cfg_fc_ph=dut.cfg_fc_ph, cfg_fc_pd=dut.cfg_fc_pd, cfg_fc_nph=dut.cfg_fc_nph, cfg_fc_npd=dut.cfg_fc_npd, cfg_fc_cplh=dut.cfg_fc_cplh, cfg_fc_cpld=dut.cfg_fc_cpld, cfg_fc_sel=dut.cfg_fc_sel, # Configuration Control Interface # cfg_hot_reset_in # cfg_hot_reset_out # cfg_config_space_enable # cfg_dsn # cfg_bus_number # cfg_ds_port_number # cfg_ds_bus_number # cfg_ds_device_number # cfg_ds_function_number # cfg_power_state_change_ack # cfg_power_state_change_interrupt cfg_err_cor_in=dut.status_error_cor, cfg_err_uncor_in=dut.status_error_uncor, # cfg_flr_in_process # cfg_flr_done # cfg_vf_flr_in_process # cfg_vf_flr_func_num # cfg_vf_flr_done # cfg_pm_aspm_l1_entry_reject # cfg_pm_aspm_tx_l0s_entry_disable # cfg_req_pm_transition_l23_ready # cfg_link_training_enable # Configuration Interrupt Controller Interface # cfg_interrupt_int # cfg_interrupt_sent # cfg_interrupt_pending cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, cfg_interrupt_msi_pending_status=dut. cfg_interrupt_msi_pending_status, cfg_interrupt_msi_pending_status_data_enable=dut. cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msix_enable # cfg_interrupt_msix_mask # cfg_interrupt_msix_vf_enable # cfg_interrupt_msix_vf_mask # cfg_interrupt_msix_address # cfg_interrupt_msix_data # cfg_interrupt_msix_int # cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending_status cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, # Configuration Extend Interface # cfg_ext_read_received # cfg_ext_write_received # cfg_ext_register_number # cfg_ext_function_number # cfg_ext_write_data # cfg_ext_write_byte_enable # cfg_ext_read_data # cfg_ext_read_data_valid ) # self.dev.log.setLevel(logging.DEBUG) self.rc.make_port().connect(self.dev) self.driver = mqnic.Driver(self.rc) self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**self.BAR0_APERTURE, ext=True, prefetch=True) # Ethernet cocotb.fork(Clock(dut.qsfp_rx_clk, 3.102, units="ns").start()) cocotb.fork(Clock(dut.qsfp_tx_clk, 3.102, units="ns").start()) self.qsfp_mac = EthMac( tx_clk=dut.qsfp_tx_clk, tx_rst=dut.qsfp_tx_rst, tx_bus=AxiStreamBus.from_prefix(dut, "qsfp_tx_axis"), tx_ptp_time=dut.qsfp_tx_ptp_time, tx_ptp_ts=dut.qsfp_tx_ptp_ts, tx_ptp_ts_valid=dut.qsfp_tx_ptp_ts_valid, rx_clk=dut.qsfp_rx_clk, rx_rst=dut.qsfp_rx_rst, rx_bus=AxiStreamBus.from_prefix(dut, "qsfp_rx_axis"), rx_ptp_time=dut.qsfp_rx_ptp_time, ifg=12, speed=100e9) dut.qspi_dq_i.setimmediatevalue(0) self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil_cms"), dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256 * 1024) self.loopback_enable = False cocotb.fork(self._run_loopback())
def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start()) # AXI self.address_space = AddressSpace() self.pool = self.address_space.create_pool(0, 0x8000_0000) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk, dut.rst) self.address_space.register_region(self.axil_master, 0x10_0000_0000) self.hw_regs = self.address_space.create_window(0x10_0000_0000, self.axil_master.size) self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, self.address_space) self.driver = mqnic.Driver() # Ethernet self.port_mac = [] eth_int_if_width = len(dut.core_inst.iface[0].port[0].rx_async_fifo_inst.m_axis_tdata) eth_clock_period = 6.4 eth_speed = 10e9 if eth_int_if_width == 64: # 10G eth_clock_period = 6.4 eth_speed = 10e9 elif eth_int_if_width == 128: # 25G eth_clock_period = 2.56 eth_speed = 25e9 elif eth_int_if_width == 512: # 100G eth_clock_period = 3.102 eth_speed = 100e9 for iface in dut.core_inst.iface: for port in iface.port: cocotb.start_soon(Clock(port.port_rx_clk, eth_clock_period, units="ns").start()) cocotb.start_soon(Clock(port.port_tx_clk, eth_clock_period, units="ns").start()) port.port_rx_rst.setimmediatevalue(0) port.port_tx_rst.setimmediatevalue(0) mac = EthMac( tx_clk=port.port_tx_clk, tx_rst=port.port_tx_rst, tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"), tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts, tx_ptp_ts=port.ptp.axis_tx_ptp_ts, tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag, tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid, rx_clk=port.port_rx_clk, rx_rst=port.port_rx_rst, rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"), rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts, ifg=12, speed=eth_speed ) self.port_mac.append(mac) dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) dut.ctrl_reg_rd_data.setimmediatevalue(0) dut.ctrl_reg_rd_wait.setimmediatevalue(0) dut.ctrl_reg_rd_ack.setimmediatevalue(0) dut.ptp_sample_clk.setimmediatevalue(0) dut.s_axis_stat_tdata.setimmediatevalue(0) dut.s_axis_stat_tid.setimmediatevalue(0) dut.s_axis_stat_tvalid.setimmediatevalue(0) self.loopback_enable = False cocotb.start_soon(self._run_loopback())