def driveIRsp(self): dut = self.dut dut.io_i_rsp_valid <= 0 while True: yield RisingEdge(dut.clk) if int(dut.io_i_rsp_ready) == 1: dut.io_i_rsp_valid <= 0 randSignal(dut.io_i_rsp_payload_instruction) if int(dut.io_i_cmd_valid) == 1 and int(dut.io_i_cmd_ready) == 1: dut.io_i_rsp_valid <= 1 dut.io_i_rsp_payload_pc <= int(dut.io_i_cmd_payload_pc) data = 0 if int(dut.io_i_cmd_payload_pc) <= 0x03FFFFFF : for i in range(0,4): data = data | (self.rom[int(dut.io_i_cmd_payload_pc) + i] << (i*8)) elif int(dut.io_i_cmd_payload_pc) <= 0x04007FFF : for i in range(0, 4): data = data | (self.ram[int(dut.io_i_cmd_payload_pc and 0x00007FFF) + i] << (i*8)) else: raise TestFailure("out of range ICmd read") if self.wrapICmdZero and int(dut.io_i_cmd_payload_pc) == 0: dut.io_i_rsp_payload_instruction <= 0xffc02e23; #01c02023 ffc02e23 elif data == 0x00000073: dut.io_i_rsp_payload_instruction <= 0xffc02e23; elif data == 0x0FF0000F: dut.io_i_rsp_payload_instruction <= 0x00000013; #TODO remove me else: dut.io_i_rsp_payload_instruction <= data;
def cmd(dut,queue): validRandomizer = BoolRandomizer() dut.io_slave0_valid <= 0 while True: yield RisingEdge(dut.io_clkA) if int(dut.io_slave0_valid) == 1 and int(dut.io_slave0_ready) == 1: queue.put(Packet(int(dut.io_slave0_payload_a),int(dut.io_slave0_payload_b))) dut.io_slave0_valid <= validRandomizer.get() randSignal(dut.io_slave0_payload_a) randSignal(dut.io_slave0_payload_b)
def stim(drivers): for i in range(100): for toidle in drivers: randSignal(toidle.write) toidle.writeenable <= 0 driver = random.choice(drivers) randSignal(driver.writeenable) yield Timer(10) if driver.writeenable == False: assertGpio("zzzzzzzz") else: assertGpio(str(driver.write))
def push(self): dut = self.dut queue = self.queue validRandomizer = BoolRandomizer() dut.io_slave0_valid <= 0 while True: yield RisingEdge(dut.clk) if int(dut.io_slave0_valid) == 1 and int(dut.io_slave0_ready) == 1: queue.put(FifoPacket(int(dut.io_slave0_payload_a), int(dut.io_slave0_payload_b))) dut.io_slave0_valid <= validRandomizer.get() randSignal(dut.io_slave0_payload_a) randSignal(dut.io_slave0_payload_b)
def stim(drivers): for i in xrange(100): for toidle in drivers: randSignal(toidle.write) toidle.writeenable <= 0 driver = random.choice(drivers) randSignal(driver.writeenable) yield Timer(10) if driver.writeenable == False: assertGpio("zzzzzzzz") else: assertGpio(str(driver.write))
def test1(dut): dut.log.info("Cocotb test boot") #random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) ref = Ref(dut) for i in range(0, 1000): randSignal(dut.enable) yield RisingEdge(dut.clk) assertEquals(ref.getGray(), dut.gray, "gray") dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") #random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) ref = Ref(dut) for i in range(0,1000): randSignal(dut.enable) yield RisingEdge(dut.clk) assertEquals(ref.getGray(),dut.gray,"gray") dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") #random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, None)) for i in range(0,1000): randSignal(dut.io_inSIntA) randSignal(dut.io_inSIntB) yield Timer(1000) ref = Ref(dut) assertEquals(dut.io_outSInt, dut.io_outSIntRef, "io_outSInt") dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) outA_ref = 0 outB_ref = 0 for i in range(0,1000): randSignal(dut.io_inA) randSignal(dut.io_inB) yield RisingEdge(dut.clk) assertEquals(outA_ref,dut.io_outA,"io_outA") assertEquals(outB_ref, dut.io_outB, "io_outB") outA_ref = truncUInt(outA_ref + int(dut.io_inA), dut.io_outA) outB_ref = truncUInt(outB_ref + int(dut.io_inB), dut.io_outB) dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() #random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, None)) for i in range(0, 1000): randSignal(dut.io_inSIntA) randSignal(dut.io_inSIntB) yield Timer(1000) ref = Ref(dut) assertEquals(dut.io_outSInt, dut.io_outSIntRef, "io_outSInt") dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") for i in xrange(100): randSignal(dut.bus_cmd_writeenable) randSignal(dut.bus_cmd_write) yield Timer(10) writeEnable = str(dut.bus_cmd_writeenable) write = str(dut.bus_cmd_write) expected = "" for i in xrange(8): if (writeEnable[i] == '0'): expected = expected + "z" else: expected = expected + str(write[i]) assert expected == str(dut.bus_cmd_read).lower() assert expected == str(dut.bus_gpio).lower() dut.log.info("Cocotb test done")
def read(self, address, sel=1): self.PADDR <= address self.PSEL <= sel self.PENABLE <= False self.PWRITE <= False randSignal(self.PWDATA) yield RisingEdge(self.clk) self.PENABLE <= True yield waitClockedCond(self.clk, lambda: self.PREADY == True) randSignal(self.PADDR) self.PSEL <= 0 randSignal(self.PENABLE) randSignal(self.PWRITE) raise ReturnValue(int(self.PRDATA))
def write(self, address, data, sel = 1): self.PADDR <= address self.PSEL <= sel self.PENABLE <= False self.PWRITE <= True self.PWDATA <= data yield RisingEdge(self.clk) self.PENABLE <= True yield waitClockedCond(self.clk, lambda : self.PREADY == True) randSignal(self.PADDR) self.PSEL <= 0 randSignal(self.PENABLE) randSignal(self.PWRITE) randSignal(self.PWDATA)
def driveIRsp(self): dut = self.dut dut.io_i_rsp_valid <= 0 while True: yield RisingEdge(dut.clk) if int(dut.io_i_rsp_ready) == 1: dut.io_i_rsp_valid <= 0 randSignal(dut.io_i_rsp_payload_instruction) if int(dut.io_i_cmd_valid) == 1 and int(dut.io_i_cmd_ready) == 1: dut.io_i_rsp_valid <= 1 dut.io_i_rsp_payload_pc <= int(dut.io_i_cmd_payload_pc) data = 0 if int(dut.io_i_cmd_payload_pc) <= 0x03FFFFFF: for i in range(0, 4): data = data | ( self.rom[int(dut.io_i_cmd_payload_pc) + i] << (i * 8)) elif int(dut.io_i_cmd_payload_pc) <= 0x04007FFF: for i in range(0, 4): data = data | (self.ram[ int(dut.io_i_cmd_payload_pc and 0x00007FFF) + i] << (i * 8)) else: raise TestFailure("out of range ICmd read") if self.wrapICmdZero and int(dut.io_i_cmd_payload_pc) == 0: dut.io_i_rsp_payload_instruction <= 0xffc02e23 #01c02023 ffc02e23 elif data == 0x00000073: dut.io_i_rsp_payload_instruction <= 0xffc02e23 elif data == 0x0FF0000F: dut.io_i_rsp_payload_instruction <= 0x00000013 #TODO remove me else: dut.io_i_rsp_payload_instruction <= data
def test1(dut): dut.log.info("Cocotb test boot") #random.seed(0) for i in range(0, 1000): randSignal(dut.io_inSFix_0) randSignal(dut.io_inSFix_1) randSignal(dut.io_inBundleA_a_sfix) randSignal(dut.io_inSFix2) yield Timer(1000) ref = Ref(dut) assertEquals(ref.io_outSFix_0, dut.io_outSFix_0, "io_outSFix_0") assertEquals(ref.io_outSFix_1, dut.io_outSFix_1, "io_outSFix_1") assertEquals(ref.io_outSFix2, dut.io_outSFix2, "io_outSFix2") assertEquals(ref.io_outBundleA_a_sfix, dut.io_outBundleA_a_sfix, "io_outBundleA_a_sfix") dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) uutModel = UutModel(dut) for i in range(0, 5000): randSignal(dut.io_bus_aw_valid) randSignal(dut.io_bus_aw_payload_addr) randSignal(dut.io_bus_w_valid) randSignal(dut.io_bus_w_payload_data) randSignal(dut.io_bus_ar_valid) randSignal(dut.io_bus_ar_payload_addr) randSignal(dut.io_bus_b_ready) randSignal(dut.io_bus_r_ready) yield RisingEdge(dut.clk) dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") # itemDir = dut.uint4.__dict__ # # for i in itemDir: # print '{0} : {1}'.format(i, itemDir[i]) for i in range(0,200): randSignal(dut.uint8) randSignal(dut.sint8) randSignal(dut.bits8) yield Timer(1000) uint8 = int(dut.uint8) sint8 = sint(dut.sint8) bits8 = int(dut.bits8) check(dut.bitsShiftLeftInt, 4, 0) check(dut.uintShiftLeftInt, 4, 0) check(dut.sintShiftLeftInt, 4, 0) check(dut.uint08ShiftLeftUint , 255, 0 << uint8) check(dut.sint08ShiftLeftUint , 255, 0 << uint8) check(dut.bits08ShiftLeftUint , 255, 0 << uint8) check(dut.uint08Equals , 1, 0 == uint8) check(dut.uint08NotEquals, 1, 0 != uint8) check(dut.uint08Add, 8, 0 + uint8) check(dut.uint08Sub, 8, 0 - uint8) check(dut.uint08Mul, 8, 0 * uint8) check(dut.uint08And, 8, 0 & uint8) check(dut.uint08Or , 8, 0 | uint8) check(dut.uint08Xor, 8, 0 ^ uint8) check(dut.uint08Smaller , 1, 0 < uint8) check(dut.uint08SmallerEquals, 1, 0 <= uint8) check(dut.uint08Bigger , 1, 0 > uint8) check(dut.uint08BiggerEquals , 1, 0 >= uint8) check(dut.sint08Equals , 1, 0 == sint8) check(dut.sint08NotEquals, 1, 0 != sint8) check(dut.sint08Add, 8, 0 + sint8) check(dut.sint08Sub, 8, 0 - sint8) check(dut.sint08Mul, 8, 0 * sint8) check(dut.sint08And, 8, 0 & sint8) check(dut.sint08Or , 8, 0 | sint8) check(dut.sint08Xor, 8, 0 ^ sint8) check(dut.sint08Smaller , 1, 0 < sint8) check(dut.sint08SmallerEquals, 1, 0 <= sint8) check(dut.sint08Bigger , 1, 0 > sint8) check(dut.sint08BiggerEquals , 1, 0 >= sint8) check(dut.bits08Equals, 1, 0 == bits8) check(dut.bits08NotEquals, 1, 0 != bits8) check(dut.bits08And, 8, 0 & bits8) check(dut.bits08Or, 8, 0 | bits8) check(dut.bits08Xor, 8, 0 ^ bits8) check(dut.uint80ShiftLeftUint , 8, uint8 << 0) check(dut.sint80ShiftLeftUint , 8, sint8 << 0) check(dut.bits80ShiftLeftUint , 8, bits8 << 0) check(dut.uint80Equals , 1, uint8 == 0) check(dut.uint80NotEquals, 1, uint8 != 0) check(dut.uint80Add, 8, uint8 + 0) check(dut.uint80Sub, 8, uint8 - 0) check(dut.uint80Mul, 8, uint8 * 0) check(dut.uint80And, 8, uint8 & 0) check(dut.uint80Or , 8, uint8 | 0) check(dut.uint80Xor, 8, uint8 ^ 0) check(dut.uint80Smaller , 1, uint8 < 0) check(dut.uint80SmallerEquals, 1, uint8 <= 0) check(dut.uint80Bigger , 1, uint8 > 0) check(dut.uint80BiggerEquals , 1, uint8 >= 0) check(dut.sint80Equals , 1, sint8 == 0) check(dut.sint80NotEquals, 1, sint8 != 0) check(dut.sint80Add, 8, sint8 + 0) check(dut.sint80Sub, 8, sint8 - 0) check(dut.sint80Mul, 8, sint8 * 0) check(dut.sint80And, 8, sint8 & 0) check(dut.sint80Or , 8, sint8 | 0) check(dut.sint80Xor, 8, sint8 ^ 0) check(dut.sint80Smaller , 1, sint8 < 0) check(dut.sint80SmallerEquals, 1, sint8 <= 0) check(dut.sint80Bigger , 1, sint8 > 0) check(dut.sint80BiggerEquals , 1, sint8 >= 0) check(dut.bits80Equals, 1, bits8 == 0) check(dut.bits80NotEquals, 1, bits8 != 0) check(dut.bits80And, 8, bits8 & 0) check(dut.bits80Or, 8, bits8 | 0) check(dut.bits80Xor, 8, bits8 ^ 0) check(dut.bitsResizeBigger,16,0) check(dut.uintResizeBigger,16,0) check(dut.sintResizeBigger,16,0) check(dut.bits08Cat, 8, bits8) check(dut.bits80Cat, 8, bits8) dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") #random.seed(0) for i in range(0,1000): randSignal(dut.io_conds_0) randSignal(dut.io_conds_1) randSignal(dut.io_conds_2) randSignal(dut.io_conds_3) randSignal(dut.io_conds_4) randSignal(dut.io_conds_5) randSignal(dut.io_conds_6) randSignal(dut.io_conds_7) randSignal(dut.io_inAA_0_a) randSignal(dut.io_inAA_0_c) randSignal(dut.io_inAA_0_b) randSignal(dut.io_inAA_0_d) randSignal(dut.io_inAA_1_a) randSignal(dut.io_inAA_1_c) randSignal(dut.io_inAA_1_b) randSignal(dut.io_inAA_1_d) randSignal(dut.io_inAA_2_a) randSignal(dut.io_inAA_2_c) randSignal(dut.io_inAA_2_b) randSignal(dut.io_inAA_2_d) randSignal(dut.io_inA_0_a) randSignal(dut.io_inA_0_c) yield Timer(1000) ref = Ref(dut) assertEquals(ref.io_outAA_a, dut.io_outAA_a, "io_outAA_a") assertEquals(ref.io_outAA_b, dut.io_outAA_b, "io_outAA_b") assertEquals(ref.io_outAA_c, dut.io_outAA_c, "io_outAA_c") assertEquals(ref.io_outAA_d, dut.io_outAA_d, "io_outAA_d") dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") #random.seed(0) for i in range(0, 1000): randSignal(dut.io_conds_0) randSignal(dut.io_conds_1) randSignal(dut.io_conds_2) randSignal(dut.io_conds_3) randSignal(dut.io_conds_4) randSignal(dut.io_conds_5) randSignal(dut.io_conds_6) randSignal(dut.io_conds_7) randSignal(dut.io_inAA_0_a) randSignal(dut.io_inAA_0_c) randSignal(dut.io_inAA_0_b) randSignal(dut.io_inAA_0_d) randSignal(dut.io_inAA_1_a) randSignal(dut.io_inAA_1_c) randSignal(dut.io_inAA_1_b) randSignal(dut.io_inAA_1_d) randSignal(dut.io_inAA_2_a) randSignal(dut.io_inAA_2_c) randSignal(dut.io_inAA_2_b) randSignal(dut.io_inAA_2_d) randSignal(dut.io_inA_0_a) randSignal(dut.io_inA_0_c) yield Timer(1000) ref = Ref(dut) assertEquals(ref.io_outAA_a, dut.io_outAA_a, "io_outAA_a") assertEquals(ref.io_outAA_b, dut.io_outAA_b, "io_outAA_b") assertEquals(ref.io_outAA_c, dut.io_outAA_c, "io_outAA_c") assertEquals(ref.io_outAA_d, dut.io_outAA_d, "io_outAA_d") dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, None)) for i in range(0,1000): randSignal(dut.io_conds_0) randSignal(dut.io_conds_1) randSignal(dut.io_conds_2) randSignal(dut.io_conds_3) randSignal(dut.io_conds_4) randSignal(dut.io_conds_5) randSignal(dut.io_conds_6) randSignal(dut.io_conds_7) randSignal(dut.io_data_0 ) randSignal(dut.io_data_1 ) randSignal(dut.io_data_2 ) randSignal(dut.io_data_3 ) randSignal(dut.io_data_4 ) randSignal(dut.io_data_5 ) randSignal(dut.io_data_6 ) randSignal(dut.io_data_7 ) randSignal(dut.io_data_8 ) randSignal(dut.io_data_9 ) randSignal(dut.io_data_10) randSignal(dut.io_data_11) yield RisingEdge(dut.clk) ref = Ref(dut) assertEquals(ref.io_outDefault,dut.io_outDefault,"io_outDefault") assertEquals(ref.io_outComplex, dut.io_outComplex, "io_outComplex") yield Timer(1) assertEquals(ref.io_outComplex, dut.io_outRegComplex, "io_outRegComplex") dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") # itemDir = dut.uint4.__dict__ # # for i in itemDir: # print '{0} : {1}'.format(i, itemDir[i]) for i in range(0,2000): randSignal(dut.uint4) randSignal(dut.uint8) randSignalNotZero(dut.uint4NotZero) randSignalNotZero(dut.uint8NotZero) randSignal(dut.uint32) randSignal(dut.sint4) randSignal(dut.sint8) randSignalNotZero(dut.sint4NotZero) randSignalNotZero(dut.sint8NotZero) randSignal(dut.sint32) randSignal(dut.bits4) randSignal(dut.bits8) randSignal(dut.bits32) randSignal(dut.boolA) randSignal(dut.boolB) randSignal(dut.boolC) yield Timer(1000) uint4 = int(dut.uint4) uint8 = int(dut.uint8) uint32 = int(dut.uint32) sint4 = sint(dut.sint4) sint8 = sint(dut.sint8) sint32 = sint(dut.sint32) bits4 = int(dut.bits4) bits8 = int(dut.bits8) bits32 = int(dut.bits32) boolA = int(dut.boolA) boolB = int(dut.boolB) boolC = int(dut.boolC) uint4NotZero = int(dut.uint4NotZero) uint8NotZero = int(dut.uint8NotZero) sint4NotZero = sint(dut.sint4NotZero) sint8NotZero = sint(dut.sint8NotZero) check(dut.boolMux,1, boolA if boolC else boolB) check(dut.bitsBsMux,8, bits8 if boolC else bits4) check(dut.uintBsMux,8, uint8 if boolC else uint4) check(dut.sintBsMux,8, sint8 if boolC else sint4) check(dut.bitsSbMux,8, bits4 if boolC else bits8) check(dut.uintSbMux,8, uint4 if boolC else uint8) check(dut.sintSbMux,8, sint4 if boolC else sint8) check(dut.stateNativeMux ,2, 0 if boolC else 1) check(dut.stateBinarySequancialMux ,2, 0 if boolC else 1) check(dut.stateBinaryOneHotMux ,3, 1 if boolC else 2) check(dut.uintNot, 4, ~uint4) check(dut.uintShiftLeftInt , 12, uint8 << 4) check(dut.uintShiftLeftUint , 23, uint8 << uint4) check(dut.uintShiftRightInt , 4, uint8 >> 4) check(dut.uintShiftRightUint, 8, uint8 >> uint4) check(dut.uintShiftLeftIntFixedWidth , 8, uint8 << 4) check(dut.uintShiftLeftUintFixedWidth , 8, uint8 << uint4) check(dut.uintShiftRightIntFixedWidth , 8, uint8 >> 4) check(dut.uintShiftRightUintFixedWidth, 8, uint8 >> uint4) check(dut.sintNot, 4, ~sint4) checkSigned(dut.sintMinus, 4, -sint4) check(dut.sintShiftLeftInt , 12, sint8 << 4) check(dut.sintShiftLeftUint , 23, sint8 << uint4) check(dut.sintShiftRightInt , 4, sint8 >> 4) checkSigned(dut.sintShiftRightUint, 8, sint8 >> uint4) check(dut.sintShiftLeftIntFixedWidth , 8, sint8 << 4) check(dut.sintShiftLeftUintFixedWidth , 8, sint8 << uint4) checkSigned(dut.sintShiftRightIntFixedWidth , 8, sint8 >> 4) checkSigned(dut.sintShiftRightUintFixedWidth, 8, sint8 >> uint4) check(dut.bitsNot, 4, ~bits4) check(dut.bitsShiftLeftInt , 12, bits8 << 4) check(dut.bitsShiftLeftUint , 23, bits8 << uint4) check(dut.bitsShiftRightInt , 4, bits8 >> 4) check(dut.bitsShiftRightUint, 8, bits8 >> uint4) check(dut.bitsShiftLeftIntFixedWidth , 8, bits8 << 4) check(dut.bitsShiftLeftUintFixedWidth , 8, bits8 << uint4) check(dut.bitsShiftRightIntFixedWidth , 8, bits8 >> 4) check(dut.bitsShiftRightUintFixedWidth, 8, bits8 >> uint4) check(dut.uintSbEquals, 1, uint4 == uint8) check(dut.uintSbNotEquals, 1, uint4 != uint8) check(dut.uintSbAdd, 8, uint4 + uint8) check(dut.uintSbSub, 8, uint4 - uint8) check(dut.uintSbMul, 12, uint4 * uint8) if uint8NotZero != 0: check(dut.uintSbDiv, 4, uint4 // uint8NotZero) check(dut.uintSbRem, 4, uint4 % uint8NotZero) check(dut.uintSbAnd, 8, uint4 & uint8) check(dut.uintSbOr , 8, uint4 | uint8) check(dut.uintSbXor, 8, uint4 ^ uint8) check(dut.uintSbSmaller , 1, uint4 < uint8) check(dut.uintSbSmallerEquals, 1, uint4 <= uint8) check(dut.uintSbBigger , 1, uint4 > uint8) check(dut.uintSbBiggerEquals , 1, uint4 >= uint8) check(dut.sintSbEquals, 1, sint4 == sint8) check(dut.sintSbNotEquals, 1, sint4 != sint8) checkSigned(dut.sintSbAdd, 8, sint4 + sint8) checkSigned(dut.sintSbSub, 8, sint4 - sint8) checkSigned(dut.sintSbMul, 12, sint4 * sint8) if sint8NotZero != 0 and sint4 > 0 and sint8NotZero > 0: checkSigned(dut.sintSbDiv, 4, int(sint4//sint8NotZero)) checkSigned(dut.sintSbRem, 4, int(sint4% sint8NotZero)) checkSigned(dut.sintSbAnd, 8, sint4 & sint8) checkSigned(dut.sintSbOr, 8, sint4 | sint8) checkSigned(dut.sintSbXor, 8, sint4 ^ sint8) check(dut.sintSbSmaller, 1, sint4 < sint8) check(dut.sintSbSmallerEquals, 1, sint4 <= sint8) check(dut.sintSbBigger, 1, sint4 > sint8) check(dut.sintSbBiggerEquals, 1, sint4 >= sint8) check(dut.bitsSbEquals, 1, bits4 == bits8) check(dut.bitsSbNotEquals, 1, bits4 != bits8) check(dut.bitsSbAnd, 8, bits4 & bits8) check(dut.bitsSbOr, 8, bits4 | bits8) check(dut.bitsSbXor, 8, bits4 ^ bits8) check(dut.uintBsEquals, 1, uint8 == uint4) check(dut.uintBsNotEquals, 1, uint8 != uint4) check(dut.uintBsAdd, 8, uint8 + uint4) check(dut.uintBsSub, 8, uint8 - uint4) check(dut.uintBsMul, 12, uint8 * uint4) if uint4NotZero != 0: check(dut.uintBsDiv, 8, uint8 // uint4NotZero) check(dut.uintBsRem, 8, uint8 % uint4NotZero) check(dut.uintBsAnd, 8, uint8 & uint4) check(dut.uintBsOr , 8, uint8 | uint4) check(dut.uintBsXor, 8, uint8 ^ uint4) check(dut.uintBsSmaller , 1, uint8 < uint4) check(dut.uintBsSmallerEquals, 1, uint8 <= uint4) check(dut.uintBsBigger , 1, uint8 > uint4) check(dut.uintBsBiggerEquals , 1, uint8 >= uint4) check(dut.sintBsEquals, 1, sint8 == sint4) check(dut.sintBsNotEquals, 1, sint8 != sint4) checkSigned(dut.sintBsAdd, 8, sint8 + sint4) checkSigned(dut.sintBsSub, 8, sint8 - sint4) checkSigned(dut.sintBsMul, 12, sint8 * sint4) if sint4NotZero != 0 and sint8 > 0 and sint4NotZero > 0: checkSigned(dut.sintBsDiv, 8, int(sint8// sint4NotZero)) checkSigned(dut.sintBsRem, 8, int(sint8% sint4NotZero)) checkSigned(dut.sintBsAnd, 8, sint8 & sint4) checkSigned(dut.sintBsOr, 8, sint8 | sint4) checkSigned(dut.sintBsXor, 8, sint8 ^ sint4) check(dut.sintBsSmaller, 1, sint8 < sint4) check(dut.sintBsSmallerEquals, 1, sint8 <= sint4) check(dut.sintBsBigger, 1, sint8 > sint4) check(dut.sintBsBiggerEquals, 1, sint8 >= sint4) check(dut.bitsBsEquals, 1, bits8 == bits4) check(dut.bitsBsNotEquals, 1, bits8 != bits4) check(dut.bitsBsAnd, 8, bits8 & bits4) check(dut.bitsBsOr, 8, bits8 | bits4) check(dut.bitsBsXor, 8, bits8 ^ bits4) check(dut.bitsCat, 12, bits8 * 16 + bits4) check(dut.boolEquals, 1, boolA == boolB) check(dut.boolNotEquals, 1, boolA != boolB) check(dut.boolAnd, 1, boolA & boolB) check(dut.boolOr, 1, boolA | boolB) check(dut.boolXor, 1, boolA ^ boolB) check(dut.uintAsBits,8,int(dut.uint8)) check(dut.uintAsSint,8,int(dut.uint8)) check(dut.sintAsBits,8,int(dut.sint8)) check(dut.sintAsUint,8,int(dut.sint8)) check(dut.bitsAsUint,8,int(dut.bits8)) check(dut.bitsAsSint,8,int(dut.bits8)) check(dut.boolAsBits,1,int(dut.boolA)) check(dut.boolAsUInt,1,int(dut.boolA)) check(dut.boolAsSInt,1,int(dut.boolA)) check(dut.bitsResizeBigger ,16,bits8) check(dut.bitsResizeSmaller ,4 ,bits8) check(dut.uintResizeBigger ,16,uint8) check(dut.uintResizeSmaller ,4 ,uint8) check(dut.sintResizeBigger ,16,sint8) check(dut.sintResizeSmaller ,4 ,sint8) bits8StateSeq = (bits8 & 3) bits8StateHO = (bits8 & 7) if bits8StateSeq <= 2: check(dut.stateNativeBits,2,bits8) check(dut.stateBinarySequancialBits, 2, bits8) check(dut.stateNativeIsA,1,bits8StateSeq == 0) check(dut.stateNativeIsB, 1, bits8StateSeq == 1) check(dut.stateNativeIsC, 1, bits8StateSeq == 2) check(dut.stateNativeIsNotA,1,bits8StateSeq != 0) check(dut.stateNativeIsNotB, 1, bits8StateSeq != 1) check(dut.stateNativeIsNotC, 1, bits8StateSeq != 2) check(dut.stateBinarySequancialIsA,1,bits8StateSeq == 0) check(dut.stateBinarySequancialIsB, 1, bits8StateSeq == 1) check(dut.stateBinarySequancialIsC, 1, bits8StateSeq == 2) check(dut.stateBinarySequancialIsNotA,1,bits8StateSeq != 0) check(dut.stateBinarySequancialIsNotB, 1, bits8StateSeq != 1) check(dut.stateBinarySequancialIsNotC, 1, bits8StateSeq != 2) if bits8StateHO == 1 or bits8StateHO == 2 or bits8StateHO == 4: check(dut.stateBinaryOneHotBits, 3, bits8) check(dut.stateBinaryOneHotIsA,1,bits8StateHO == 1) check(dut.stateBinaryOneHotIsB, 1, bits8StateHO == 2) check(dut.stateBinaryOneHotIsC, 1, bits8StateHO == 4) check(dut.stateBinaryOneHotIsNotA,1,bits8StateHO != 1) check(dut.stateBinaryOneHotIsNotB, 1, bits8StateHO != 2) check(dut.stateBinaryOneHotIsNotC, 1, bits8StateHO != 4) check(dut.bitsAggregateFixed, 8, (3 << 5) | ((bits8 & 3) << 3) |(boolA << 2) | (boolA << 1) | (1 << 0)) check(dut.uintAggregateFixed, 8, (3 << 5) | ((uint8 & 3) << 3) |(boolA << 2) | (boolA << 1) | (1 << 0)) check(dut.sintAggregateFixed, 8, (3 << 5) | ((sint8 & 3) << 3) |(boolA << 2) | (boolA << 1) | (1 << 0)) check(dut.bitsAggregateUnfixedWidthFixedDefault, 8, (3 << 5) | ((bits8 & 3) << 3) |(boolA << 2) | (3 << 1) | (1 << 0)) check(dut.uintAggregateUnfixedWidthFixedDefault, 8, (3 << 5) | ((uint8 & 3) << 3) |(boolA << 2) | (3 << 1) | (1 << 0)) check(dut.sintAggregateUnfixedWidthFixedDefault, 8, (3 << 5) | ((sint8 & 3) << 3) |(boolA << 2) | (3 << 1) | (1 << 0)) check(dut.bitsAggregateUnfixedWidthUnfixedDefault, 8, (3 << 5) | ((bits8 & 3) << 3) |(boolA << 2) | (boolA << 1) | (1 << 0)) check(dut.uintAggregateUnfixedWidthUnfixedDefault, 8, (3 << 5) | ((uint8 & 3) << 3) |(boolA << 2) | (boolA << 1) | (1 << 0)) check(dut.sintAggregateUnfixedWidthUnfixedDefault, 8, (3 << 5) | ((sint8 & 3) << 3) |(boolA << 2) | (boolA << 1) | (1 << 0)) bits27 = bits32 & ((1 << 27) - 1) uint5 = uint8 & 0x1F uint5mod27 = uint5 % 27 rotateLeftValue = (bits27 << uint5mod27) | (bits27 >> (27-uint5mod27)) rotateRightValue = (bits27 >> uint5mod27) | (bits27 << (27-uint5mod27)) check(dut.bitsRotateLeftUInt,27,rotateLeftValue) check(dut.uintRotateLeftUInt, 27, rotateLeftValue) check(dut.sintRotateLeftUInt, 27, rotateLeftValue) check(dut.bitsRotateRightUInt,27,rotateRightValue) check(dut.uintRotateRightUInt, 27, rotateRightValue) check(dut.sintRotateRightUInt, 27, rotateRightValue) dut.log.info("Cocotb test done")
def driveDRsp(self): logg = open('log.txt', 'wb') dut = self.dut dut.io_d_rsp_valid <= 0 counter = 0 while True: yield RisingEdge(dut.clk) counter = counter + 1 if int(dut.io_d_rsp_ready) == 1 : dut.io_d_rsp_valid <= 0 randSignal(dut.io_d_rsp_payload) if int(dut.io_d_cmd_valid) == 1 and int(dut.io_d_cmd_ready) == 1 : if int(dut.io_d_cmd_payload_wr) == 1 : if int(dut.io_d_cmd_payload_address) == 0xF0000000 : logg.write(str(chr(int(dut.io_d_cmd_payload_data) & 0xFF))) elif int(dut.io_d_cmd_payload_address) == 0xF0000004 : pass elif int(dut.io_d_cmd_payload_address) == 0xFFFFFFF8 : pass elif int(dut.io_d_cmd_payload_address) == 0xF0000010 : pass elif int(dut.io_d_cmd_payload_address) == 0xF0000044 : pass elif int(dut.io_d_cmd_payload_address) == 0xFFFFFFFC : pass elif int(dut.io_d_cmd_payload_address) <= 0x03FFFFFF : if not self.allowRomWrite: raise TestFailure("Rom was written :(") for i in range(0,1 << int(dut.io_d_cmd_payload_size)): self.rom[int(dut.io_d_cmd_payload_address) + i] = (int(dut.io_d_cmd_payload_data) >> (i*8)) & 0xFF elif int(dut.io_d_cmd_payload_address) <= 0x04007FFF : # print("write %x %x" % (int(dut.io_d_cmd_payload_address),int(dut.io_d_cmd_payload_data))) for i in range(0,1 << int(dut.io_d_cmd_payload_size)): self.ram[(int(dut.io_d_cmd_payload_address) & 0x00007FFF) + i] = (int(dut.io_d_cmd_payload_data) >> (i*8)) & 0xFF else: raise TestFailure("dCmd out of range %x" %(int(dut.io_d_cmd_payload_address))) else: dut.io_d_rsp_valid <= 1 if int(dut.io_d_cmd_payload_address) == 0xF0000040 : dut.io_d_rsp_payload <= counter elif int(dut.io_d_cmd_payload_address) == 0xF0000020 : dut.io_d_rsp_payload <= 0 elif int(dut.io_d_cmd_payload_address) == 0xF0000000 : dut.io_d_rsp_payload <= 0 elif int(dut.io_d_cmd_payload_address) == 0xF0000004 : dut.io_d_rsp_payload <= 0xFFFF0000 elif int(dut.io_d_cmd_payload_address) <= 0x03FFFFFF : data = 0 for i in range(0,4): data |= self.rom[int(dut.io_d_cmd_payload_address) + i] << (i*8) dut.io_d_rsp_payload <= data elif int(dut.io_d_cmd_payload_address) <= 0x04007FFF : data = 0 for i in range(0, 4): data |= self.ram[(int(dut.io_d_cmd_payload_address) & 0x00007FFF) + i] << (i*8) # print("read %x %x" % (int(dut.io_d_cmd_payload_address), int(dut.io_d_cmd_payload_data))) dut.io_d_rsp_payload <= data else: raise TestFailure("dCmd out of range %x" %(int(dut.io_d_cmd_payload_address))) if int(dut.io_iCheck_valid) == 1 : if (int(dut.io_iCheck_payload_address) & 3) != 0: raise TestFailure("iCmd bad allignement") if int(dut.io_iCheck_payload_data) != 0x00000013 and int(dut.io_iCheck_payload_data) != 0x01c02023 and int(dut.io_iCheck_payload_data) != 0xffc02e23 : for i in range(0,4): if self.rom[int(dut.io_iCheck_payload_address)+i] != ((int(dut.io_iCheck_payload_data) >> (i*8)) & 0xFF): raise TestFailure("wrong instruction read")
def test1(dut): dut.log.info("Cocotb test boot") # itemDir = dut.uint4.__dict__ # # for i in itemDir: # print '{0} : {1}'.format(i, itemDir[i]) for i in range(0,2000): randSignal(dut.uint4) randSignal(dut.uint8) randSignal(dut.sint4) randSignal(dut.sint8) randSignal(dut.bits4) randSignal(dut.bits8) randSignal(dut.boolA) randSignal(dut.boolB) randSignal(dut.boolC) yield Timer(1000) uint4 = int(dut.uint4) uint8 = int(dut.uint8) sint4 = sint(dut.sint4) sint8 = sint(dut.sint8) bits4 = int(dut.bits4) bits8 = int(dut.bits8) boolA = int(dut.boolA) boolB = int(dut.boolB) boolC = int(dut.boolC) check(dut.boolMux,1, boolA if boolC else boolB) check(dut.bitsBsMux,8, bits8 if boolC else bits4) check(dut.uintBsMux,8, uint8 if boolC else uint4) check(dut.sintBsMux,8, sint8 if boolC else sint4) check(dut.bitsSbMux,8, bits4 if boolC else bits8) check(dut.uintSbMux,8, uint4 if boolC else uint8) check(dut.sintSbMux,8, sint4 if boolC else sint8) check(dut.stateNativeMux ,2, 0 if boolC else 1) check(dut.stateBinarySequancialMux ,2, 0 if boolC else 1) check(dut.stateBinaryOneHotMux ,3, 1 if boolC else 2) check(dut.uintNot, 4, ~uint4) check(dut.uintShiftLeftInt , 12, uint8 << 4) check(dut.uintShiftLeftUint , 23, uint8 << uint4) check(dut.uintShiftRightInt , 4, uint8 >> 4) check(dut.uintShiftRightUint, 8, uint8 >> uint4) check(dut.sintNot, 4, ~sint4) checkSigned(dut.sintMinus, 4, -sint4) check(dut.sintShiftLeftInt , 12, sint8 << 4) check(dut.sintShiftLeftUint , 23, sint8 << uint4) check(dut.sintShiftRightInt , 4, sint8 >> 4) check(dut.sintShiftRightUint, 8, sint8 >> uint4) check(dut.bitsNot, 4, ~bits4) check(dut.bitsShiftLeftInt , 12, bits8 << 4) check(dut.bitsShiftLeftUint , 23, bits8 << uint4) check(dut.bitsShiftRightInt , 4, bits8 >> 4) check(dut.bitsShiftRightUint, 8, bits8 >> uint4) check(dut.uintSbEquals, 1, uint4 == uint8) check(dut.uintSbNotEquals, 1, uint4 != uint8) check(dut.uintSbAdd, 8, uint4 + uint8) check(dut.uintSbSub, 8, uint4 - uint8) check(dut.uintSbMul, 12, uint4 * uint8) if uint8 != 0: check(dut.uintSbDiv, 4, uint4 / uint8) check(dut.uintSbRem, 4, uint4 % uint8) check(dut.uintSbAnd, 8, uint4 & uint8) check(dut.uintSbOr , 8, uint4 | uint8) check(dut.uintSbXor, 8, uint4 ^ uint8) check(dut.uintSbSmaller , 1, uint4 < uint8) check(dut.uintSbSmallerEquals, 1, uint4 <= uint8) check(dut.uintSbBigger , 1, uint4 > uint8) check(dut.uintSbBiggerEquals , 1, uint4 >= uint8) check(dut.sintSbEquals, 1, sint4 == sint8) check(dut.sintSbNotEquals, 1, sint4 != sint8) checkSigned(dut.sintSbAdd, 8, sint4 + sint8) checkSigned(dut.sintSbSub, 8, sint4 - sint8) checkSigned(dut.sintSbMul, 12, sint4 * sint8) if sint8 != 0 and sint4 > 0 and sint8 > 0: checkSigned(dut.sintSbDiv, 4, int(sint4//sint8)) checkSigned(dut.sintSbRem, 4, int(sint4%sint8)) checkSigned(dut.sintSbAnd, 8, sint4 & sint8) checkSigned(dut.sintSbOr, 8, sint4 | sint8) checkSigned(dut.sintSbXor, 8, sint4 ^ sint8) check(dut.sintSbSmaller, 1, sint4 < sint8) check(dut.sintSbSmallerEquals, 1, sint4 <= sint8) check(dut.sintSbBigger, 1, sint4 > sint8) check(dut.sintSbBiggerEquals, 1, sint4 >= sint8) check(dut.bitsSbEquals, 1, bits4 == bits8) check(dut.bitsSbNotEquals, 1, bits4 != bits8) check(dut.bitsSbAnd, 8, bits4 & bits8) check(dut.bitsSbOr, 8, bits4 | bits8) check(dut.bitsSbXor, 8, bits4 ^ bits8) check(dut.uintBsEquals, 1, uint8 == uint4) check(dut.uintBsNotEquals, 1, uint8 != uint4) check(dut.uintBsAdd, 8, uint8 + uint4) check(dut.uintBsSub, 8, uint8 - uint4) check(dut.uintBsMul, 12, uint8 * uint4) if uint4 != 0: check(dut.uintBsDiv, 8, uint8 / uint4) check(dut.uintBsRem, 8, uint8 % uint4) check(dut.uintBsAnd, 8, uint8 & uint4) check(dut.uintBsOr , 8, uint8 | uint4) check(dut.uintBsXor, 8, uint8 ^ uint4) check(dut.uintBsSmaller , 1, uint8 < uint4) check(dut.uintBsSmallerEquals, 1, uint8 <= uint4) check(dut.uintBsBigger , 1, uint8 > uint4) check(dut.uintBsBiggerEquals , 1, uint8 >= uint4) check(dut.sintBsEquals, 1, sint8 == sint4) check(dut.sintBsNotEquals, 1, sint8 != sint4) checkSigned(dut.sintBsAdd, 8, sint8 + sint4) checkSigned(dut.sintBsSub, 8, sint8 - sint4) checkSigned(dut.sintBsMul, 12, sint8 * sint4) if sint4 != 0 and sint8 > 0 and sint4 > 0: checkSigned(dut.sintBsDiv, 8, int(sint8//sint4)) checkSigned(dut.sintBsRem, 8, int(sint8%sint4)) checkSigned(dut.sintBsAnd, 8, sint8 & sint4) checkSigned(dut.sintBsOr, 8, sint8 | sint4) checkSigned(dut.sintBsXor, 8, sint8 ^ sint4) check(dut.sintBsSmaller, 1, sint8 < sint4) check(dut.sintBsSmallerEquals, 1, sint8 <= sint4) check(dut.sintBsBigger, 1, sint8 > sint4) check(dut.sintBsBiggerEquals, 1, sint8 >= sint4) check(dut.bitsBsEquals, 1, bits8 == bits4) check(dut.bitsBsNotEquals, 1, bits8 != bits4) check(dut.bitsBsAnd, 8, bits8 & bits4) check(dut.bitsBsOr, 8, bits8 | bits4) check(dut.bitsBsXor, 8, bits8 ^ bits4) check(dut.bitsCat, 12, bits8 * 16 + bits4) check(dut.boolEquals, 1, boolA == boolB) check(dut.boolNotEquals, 1, boolA != boolB) check(dut.boolAnd, 1, boolA & boolB) check(dut.boolOr, 1, boolA | boolB) check(dut.boolXor, 1, boolA ^ boolB) check(dut.uintAsBits,8,int(dut.uint8)) check(dut.uintAsSint,8,int(dut.uint8)) check(dut.sintAsBits,8,int(dut.sint8)) check(dut.sintAsUint,8,int(dut.sint8)) check(dut.bitsAsUint,8,int(dut.bits8)) check(dut.bitsAsSint,8,int(dut.bits8)) check(dut.boolAsBits,1,int(dut.boolA)) check(dut.boolAsUInt,1,int(dut.boolA)) check(dut.boolAsSInt,1,int(dut.boolA)) check(dut.bitsResizeBigger ,16,bits8) check(dut.bitsResizeSmaller ,4 ,bits8) check(dut.uintResizeBigger ,16,uint8) check(dut.uintResizeSmaller ,4 ,uint8) check(dut.sintResizeBigger ,16,sint8) check(dut.sintResizeSmaller ,4 ,sint8) bits8StateSeq = (bits8 & 3) bits8StateHO = (bits8 & 7) if bits8StateSeq <= 2: check(dut.stateNativeBits,2,bits8) check(dut.stateBinarySequancialBits, 2, bits8) check(dut.stateNativeIsA,1,bits8StateSeq == 0) check(dut.stateNativeIsB, 1, bits8StateSeq == 1) check(dut.stateNativeIsC, 1, bits8StateSeq == 2) check(dut.stateNativeIsNotA,1,bits8StateSeq != 0) check(dut.stateNativeIsNotB, 1, bits8StateSeq != 1) check(dut.stateNativeIsNotC, 1, bits8StateSeq != 2) check(dut.stateBinarySequancialIsA,1,bits8StateSeq == 0) check(dut.stateBinarySequancialIsB, 1, bits8StateSeq == 1) check(dut.stateBinarySequancialIsC, 1, bits8StateSeq == 2) check(dut.stateBinarySequancialIsNotA,1,bits8StateSeq != 0) check(dut.stateBinarySequancialIsNotB, 1, bits8StateSeq != 1) check(dut.stateBinarySequancialIsNotC, 1, bits8StateSeq != 2) if bits8StateHO == 1 or bits8StateHO == 2 or bits8StateHO == 4: check(dut.stateBinaryOneHotBits, 3, bits8) check(dut.stateBinaryOneHotIsA,1,bits8StateHO == 1) check(dut.stateBinaryOneHotIsB, 1, bits8StateHO == 2) check(dut.stateBinaryOneHotIsC, 1, bits8StateHO == 4) check(dut.stateBinaryOneHotIsNotA,1,bits8StateHO != 1) check(dut.stateBinaryOneHotIsNotB, 1, bits8StateHO != 2) check(dut.stateBinaryOneHotIsNotC, 1, bits8StateHO != 4) # B(7 -> false,(6 downto 5) -> true,(4 downto 3) -> bits8(1 downto 0),(2 downto 1) -> boolA,0 -> True) aggregateValue = (3 << 5) | ((bits8 & 3) << 3) |(boolA << 2) | (boolA << 1) | (1 << 0) check(dut.bitsAggregateFixed, 8, aggregateValue) check(dut.uintAggregateFixed, 8, aggregateValue) check(dut.sintAggregateFixed, 8, aggregateValue) aggregateValue = (3 << 5) | ((bits8 & 3) << 3) |(boolA << 2) | (3 << 1) | (1 << 0) check(dut.bitsAggregateUnfixedWidthFixedDefault, 8, aggregateValue) check(dut.uintAggregateUnfixedWidthFixedDefault, 8, aggregateValue) check(dut.sintAggregateUnfixedWidthFixedDefault, 8, aggregateValue) aggregateValue = (3 << 5) | ((bits8 & 3) << 3) |(boolA << 2) | (boolA << 1) | (1 << 0) check(dut.bitsAggregateUnfixedWidthUnfixedDefault, 8, aggregateValue) check(dut.uintAggregateUnfixedWidthUnfixedDefault, 8, aggregateValue) check(dut.sintAggregateUnfixedWidthUnfixedDefault, 8, aggregateValue) dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") #random.seed(0) for i in range(0, 1000): randSignal(dut.io_conds_0) randSignal(dut.io_conds_1) randSignal(dut.io_conds_2) randSignal(dut.io_conds_3) randSignal(dut.io_conds_4) randSignal(dut.io_conds_5) randSignal(dut.io_conds_6) randSignal(dut.io_conds_7) randSignal(dut.io_inAA_bod_gggg) randSignal(dut.io_inAA_bod_aosi) randSignal(dut.io_inAA_ahe) randSignal(dut.io_inAA_zwg) randSignal(dut.io_inAA_vsw) randSignal(dut.io_inAA_lwee) randSignal(dut.io_inAABits) randSignal(dut.io_inUIntA) randSignal(dut.io_inUIntB) randSignal(dut.io_assign_sel_0) randSignal(dut.io_assign_sel_1) randSignal(dut.io_assign_sel_2) randSignal(dut.io_assign_sel_3) yield Timer(1000) ref = Ref(dut) assertEquals(ref.io_complexLiteral, dut.io_complexLiteral, "io_complexLiteral") assertEquals(ref.io_outAA_bod_gggg, dut.io_outAA_bod_gggg, "io_outAA_bod_gggg") assertEquals(ref.io_outAA_bod_aosi, dut.io_outAA_bod_aosi, "io_outAA_bod_aosi") assertEquals(ref.io_outAA_ahe, dut.io_outAA_ahe, "io_outAA_ahe") assertEquals(ref.io_outAA_zwg, dut.io_outAA_zwg, "io_outAA_zwg") assertEquals(ref.io_outAA_vsw, dut.io_outAA_vsw, "io_outAA_vsw") assertEquals(ref.io_outAA_lwee, dut.io_outAA_lwee, "io_outAA_lwee") assertEquals(ref.io_outAABits, dut.io_outAABits, "io_outAABits") assertEquals(ref.io_outUIntAdder, dut.io_outUIntAdder, "io_outUIntAdder") assertEquals(ref.io_assign_bitDemux, dut.io_assign_bitDemux, "io_assign_bitDemux") dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) uutModel = UutModel(dut) for i in range(0,5000): randSignal(dut.io_bus_aw_valid) randSignal(dut.io_bus_aw_payload_addr) randSignal(dut.io_bus_w_valid) randSignal(dut.io_bus_w_payload_data) randSignal(dut.io_bus_ar_valid) randSignal(dut.io_bus_ar_payload_addr) randSignal(dut.io_bus_b_ready) randSignal(dut.io_bus_r_ready) yield RisingEdge(dut.clk) dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") # itemDir = dut.uint4.__dict__ # # for i in itemDir: # print '{0} : {1}'.format(i, itemDir[i]) for i in range(0, 200): randSignal(dut.uint8) randSignal(dut.sint8) randSignal(dut.bits8) yield Timer(1000) uint8 = int(dut.uint8) sint8 = sint(dut.sint8) bits8 = int(dut.bits8) check(dut.bitsShiftLeftInt, 4, 0) check(dut.uintShiftLeftInt, 4, 0) check(dut.sintShiftLeftInt, 4, 0) check(dut.uint08ShiftLeftUint, 255, 0 << uint8) check(dut.sint08ShiftLeftUint, 255, 0 << uint8) check(dut.bits08ShiftLeftUint, 255, 0 << uint8) check(dut.uint08Equals, 1, 0 == uint8) check(dut.uint08NotEquals, 1, 0 != uint8) check(dut.uint08Add, 8, 0 + uint8) check(dut.uint08Sub, 8, 0 - uint8) check(dut.uint08Mul, 8, 0 * uint8) check(dut.uint08And, 8, 0 & uint8) check(dut.uint08Or, 8, 0 | uint8) check(dut.uint08Xor, 8, 0 ^ uint8) check(dut.uint08Smaller, 1, 0 < uint8) check(dut.uint08SmallerEquals, 1, 0 <= uint8) check(dut.uint08Bigger, 1, 0 > uint8) check(dut.uint08BiggerEquals, 1, 0 >= uint8) check(dut.sint08Equals, 1, 0 == sint8) check(dut.sint08NotEquals, 1, 0 != sint8) check(dut.sint08Add, 8, 0 + sint8) check(dut.sint08Sub, 8, 0 - sint8) check(dut.sint08Mul, 8, 0 * sint8) check(dut.sint08And, 8, 0 & sint8) check(dut.sint08Or, 8, 0 | sint8) check(dut.sint08Xor, 8, 0 ^ sint8) check(dut.sint08Smaller, 1, 0 < sint8) check(dut.sint08SmallerEquals, 1, 0 <= sint8) check(dut.sint08Bigger, 1, 0 > sint8) check(dut.sint08BiggerEquals, 1, 0 >= sint8) check(dut.bits08Equals, 1, 0 == bits8) check(dut.bits08NotEquals, 1, 0 != bits8) check(dut.bits08And, 8, 0 & bits8) check(dut.bits08Or, 8, 0 | bits8) check(dut.bits08Xor, 8, 0 ^ bits8) check(dut.uint80ShiftLeftUint, 8, uint8 << 0) check(dut.sint80ShiftLeftUint, 8, sint8 << 0) check(dut.bits80ShiftLeftUint, 8, bits8 << 0) check(dut.uint80Equals, 1, uint8 == 0) check(dut.uint80NotEquals, 1, uint8 != 0) check(dut.uint80Add, 8, uint8 + 0) check(dut.uint80Sub, 8, uint8 - 0) check(dut.uint80Mul, 8, uint8 * 0) check(dut.uint80And, 8, uint8 & 0) check(dut.uint80Or, 8, uint8 | 0) check(dut.uint80Xor, 8, uint8 ^ 0) check(dut.uint80Smaller, 1, uint8 < 0) check(dut.uint80SmallerEquals, 1, uint8 <= 0) check(dut.uint80Bigger, 1, uint8 > 0) check(dut.uint80BiggerEquals, 1, uint8 >= 0) check(dut.sint80Equals, 1, sint8 == 0) check(dut.sint80NotEquals, 1, sint8 != 0) check(dut.sint80Add, 8, sint8 + 0) check(dut.sint80Sub, 8, sint8 - 0) check(dut.sint80Mul, 8, sint8 * 0) check(dut.sint80And, 8, sint8 & 0) check(dut.sint80Or, 8, sint8 | 0) check(dut.sint80Xor, 8, sint8 ^ 0) check(dut.sint80Smaller, 1, sint8 < 0) check(dut.sint80SmallerEquals, 1, sint8 <= 0) check(dut.sint80Bigger, 1, sint8 > 0) check(dut.sint80BiggerEquals, 1, sint8 >= 0) check(dut.bits80Equals, 1, bits8 == 0) check(dut.bits80NotEquals, 1, bits8 != 0) check(dut.bits80And, 8, bits8 & 0) check(dut.bits80Or, 8, bits8 | 0) check(dut.bits80Xor, 8, bits8 ^ 0) check(dut.bitsResizeBigger, 16, 0) check(dut.uintResizeBigger, 16, 0) check(dut.sintResizeBigger, 16, 0) check(dut.bits08Cat, 8, bits8) check(dut.bits80Cat, 8, bits8) dut.log.info("Cocotb test done")
def driveDRsp(self): logg = open('log.txt', 'wb') dut = self.dut dut.io_d_rsp_valid <= 0 counter = 0 while True: yield RisingEdge(dut.clk) counter = counter + 1 if int(dut.io_d_rsp_ready) == 1: dut.io_d_rsp_valid <= 0 randSignal(dut.io_d_rsp_payload) if int(dut.io_d_cmd_valid) == 1 and int(dut.io_d_cmd_ready) == 1: if int(dut.io_d_cmd_payload_wr) == 1: if int(dut.io_d_cmd_payload_address) == 0xF0000000: logg.write( str(chr(int(dut.io_d_cmd_payload_data) & 0xFF))) elif int(dut.io_d_cmd_payload_address) == 0xF0000004: pass elif int(dut.io_d_cmd_payload_address) == 0xFFFFFFF8: pass elif int(dut.io_d_cmd_payload_address) == 0xF0000010: pass elif int(dut.io_d_cmd_payload_address) == 0xF0000044: pass elif int(dut.io_d_cmd_payload_address) == 0xFFFFFFFC: pass elif int(dut.io_d_cmd_payload_address) <= 0x03FFFFFF: if not self.allowRomWrite: raise TestFailure("Rom was written :(") for i in range(0, 1 << int(dut.io_d_cmd_payload_size)): self.rom[int(dut.io_d_cmd_payload_address) + i] = (int(dut.io_d_cmd_payload_data) >> (i * 8)) & 0xFF elif int(dut.io_d_cmd_payload_address) <= 0x04007FFF: # print("write %x %x" % (int(dut.io_d_cmd_payload_address),int(dut.io_d_cmd_payload_data))) for i in range(0, 1 << int(dut.io_d_cmd_payload_size)): self.ram[(int(dut.io_d_cmd_payload_address) & 0x00007FFF) + i] = (int(dut.io_d_cmd_payload_data) >> (i * 8)) & 0xFF else: raise TestFailure("dCmd out of range %x" % (int(dut.io_d_cmd_payload_address))) else: dut.io_d_rsp_valid <= 1 if int(dut.io_d_cmd_payload_address) == 0xF0000040: dut.io_d_rsp_payload <= counter elif int(dut.io_d_cmd_payload_address) == 0xF0000020: dut.io_d_rsp_payload <= 0 elif int(dut.io_d_cmd_payload_address) == 0xF0000000: dut.io_d_rsp_payload <= 0 elif int(dut.io_d_cmd_payload_address) == 0xF0000004: dut.io_d_rsp_payload <= 0xFFFF0000 elif int(dut.io_d_cmd_payload_address) <= 0x03FFFFFF: data = 0 for i in range(0, 4): data |= self.rom[int(dut.io_d_cmd_payload_address) + i] << (i * 8) dut.io_d_rsp_payload <= data elif int(dut.io_d_cmd_payload_address) <= 0x04007FFF: data = 0 for i in range(0, 4): data |= self.ram[(int(dut.io_d_cmd_payload_address) & 0x00007FFF) + i] << (i * 8) # print("read %x %x" % (int(dut.io_d_cmd_payload_address), int(dut.io_d_cmd_payload_data))) dut.io_d_rsp_payload <= data else: raise TestFailure("dCmd out of range %x" % (int(dut.io_d_cmd_payload_address))) if int(dut.io_iCheck_valid) == 1: if (int(dut.io_iCheck_payload_address) & 3) != 0: raise TestFailure("iCmd bad allignement") if int(dut.io_iCheck_payload_data) != 0x00000013 and int( dut.io_iCheck_payload_data) != 0x01c02023 and int( dut.io_iCheck_payload_data) != 0xffc02e23: for i in range(0, 4): if self.rom[int(dut.io_iCheck_payload_address) + i] != ((int(dut.io_iCheck_payload_data) >> (i * 8)) & 0xFF): raise TestFailure("wrong instruction read")